mvreg_read
val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id));
win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE);
win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE);
val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
val = mvreg_read(pp, MVNETA_RXQ_CMD);
val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
val = mvreg_read(pp, MVNETA_TXQ_CMD);
val = mvreg_read(pp, MVNETA_PORT_STATUS);
val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
val = mvreg_read(pp, MVNETA_TX_MTU);
val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
val = mvreg_read(pp, MVNETA_TYPE_PRIO);
u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
old_an = an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4);
while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
lpi1 = mvreg_read(pp, MVNETA_LPI_CTRL_1);
status = mvreg_read(pp, MVNETA_GMAC_STATUS);
lpi0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
lpi1 = mvreg_read(pp, MVNETA_LPI_CTRL_1);
txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) &
u32 val = mvreg_read(pp, MVNETA_VLAN_PRIO_TO_RXQ);
val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG);
u32 val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG);
mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);
mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);
val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));