mt312_writereg
return mt312_writereg(state, RESET, full ? 0x80 : 0x40);
ret = mt312_writereg(state, MON_CTRL, 0x03);
ret = mt312_writereg(state, MON_CTRL, 0x05);
ret = mt312_writereg(state, CONFIG,
ret = mt312_writereg(state, GPP_CTRL, 0x80);
ret = mt312_writereg(state, HW_CTRL, 0x00);
ret = mt312_writereg(state, MPEG_CTRL, 0x00);
ret = mt312_writereg(state, SNR_THS_HIGH, 0x32);
ret = mt312_writereg(state, OP_CTRL, buf[0]);
ret = mt312_writereg(state, CS_SW_LIM, 0x69);
ret = mt312_writereg(state, DISEQC_MODE,
ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40));
ret = mt312_writereg(state, DISEQC_MODE,
ret = mt312_writereg(state, DISEQC_MODE,
return mt312_writereg(state, DISEQC_MODE, val);
ret = mt312_writereg(state, GPP_CTRL, val);
ret = mt312_writereg(state, GPP_CTRL, 0x00);
ret = mt312_writereg(state, HW_CTRL, 0x0d);
ret = mt312_writereg(state, CONFIG, config & 0x7f);