mvpp2_prs_sram_shift_set
mvpp2_prs_sram_shift_set(&pe, -12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN,
mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_EDSA_LEN,
mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN +
mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN +
mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
mvpp2_prs_sram_shift_set(&pe, -12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
mvpp2_prs_sram_shift_set(&pe, shift,
mvpp2_prs_sram_shift_set(&pe, 2 + MVPP2_ETH_TYPE_LEN + shift,
mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN,