drivers/gpu/drm/msm/msm_drv.h

46

struct msm_mdss;

drivers/gpu/drm/msm/msm_mdss.c

106

struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd);

drivers/gpu/drm/msm/msm_mdss.c

110

clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);

drivers/gpu/drm/msm/msm_mdss.c

117

struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd);

drivers/gpu/drm/msm/msm_mdss.c

121

set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);

drivers/gpu/drm/msm/msm_mdss.c

137

struct msm_mdss *msm_mdss = domain->host_data;

drivers/gpu/drm/msm/msm_mdss.c

142

return irq_set_chip_data(irq, msm_mdss);

drivers/gpu/drm/msm/msm_mdss.c

150

static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss)

drivers/gpu/drm/msm/msm_mdss.c

155

dev = msm_mdss->dev;

drivers/gpu/drm/msm/msm_mdss.c

157

domain = irq_domain_create_linear(dev_fwnode(dev), 32, &msm_mdss_irqdomain_ops, msm_mdss);

drivers/gpu/drm/msm/msm_mdss.c

163

msm_mdss->irq_controller.enabled_mask = 0;

drivers/gpu/drm/msm/msm_mdss.c

164

msm_mdss->irq_controller.domain = domain;

drivers/gpu/drm/msm/msm_mdss.c

169

static void msm_mdss_4x_setup_ubwc(struct msm_mdss *msm_mdss)

drivers/gpu/drm/msm/msm_mdss.c

171

const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;

drivers/gpu/drm/msm/msm_mdss.c

178

writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);

drivers/gpu/drm/msm/msm_mdss.c

181

static void msm_mdss_5x_setup_ubwc(struct msm_mdss *msm_mdss)

drivers/gpu/drm/msm/msm_mdss.c

183

const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;

drivers/gpu/drm/msm/msm_mdss.c

196

writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);

drivers/gpu/drm/msm/msm_mdss.c

199

static void msm_mdss_6x_setup_ubwc(struct msm_mdss *msm_mdss)

drivers/gpu/drm/msm/msm_mdss.c

201

const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;

drivers/gpu/drm/msm/msm_mdss.c

214

writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);

drivers/gpu/drm/msm/msm_mdss.c

222

msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);

drivers/gpu/drm/msm/msm_mdss.c

223

writel_relaxed(prediction_mode, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);

drivers/gpu/drm/msm/msm_mdss.c

231

static int msm_mdss_enable(struct msm_mdss *msm_mdss)

drivers/gpu/drm/msm/msm_mdss.c

241

for (i = 0; i < msm_mdss->num_mdp_paths; i++)

drivers/gpu/drm/msm/msm_mdss.c

242

icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW));

drivers/gpu/drm/msm/msm_mdss.c

244

icc_set_bw(msm_mdss->reg_bus_path, 0,

drivers/gpu/drm/msm/msm_mdss.c

245

msm_mdss->reg_bus_bw);

drivers/gpu/drm/msm/msm_mdss.c

255

ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks);

drivers/gpu/drm/msm/msm_mdss.c

257

dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret);

drivers/gpu/drm/msm/msm_mdss.c

265

if (msm_mdss->is_mdp5 || !msm_mdss->mdss_data)

drivers/gpu/drm/msm/msm_mdss.c

268

hw_rev = readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_VERSION);

drivers/gpu/drm/msm/msm_mdss.c

271

msm_mdss_6x_setup_ubwc(msm_mdss);

drivers/gpu/drm/msm/msm_mdss.c

273

msm_mdss_5x_setup_ubwc(msm_mdss);

drivers/gpu/drm/msm/msm_mdss.c

275

msm_mdss_4x_setup_ubwc(msm_mdss);

drivers/gpu/drm/msm/msm_mdss.c

281

static int msm_mdss_disable(struct msm_mdss *msm_mdss)

drivers/gpu/drm/msm/msm_mdss.c

285

clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks);

drivers/gpu/drm/msm/msm_mdss.c

287

for (i = 0; i < msm_mdss->num_mdp_paths; i++)

drivers/gpu/drm/msm/msm_mdss.c

288

icc_set_bw(msm_mdss->mdp_path[i], 0, 0);

drivers/gpu/drm/msm/msm_mdss.c

290

if (msm_mdss->reg_bus_path)

drivers/gpu/drm/msm/msm_mdss.c

291

icc_set_bw(msm_mdss->reg_bus_path, 0, 0);

drivers/gpu/drm/msm/msm_mdss.c

296

static void msm_mdss_destroy(struct msm_mdss *msm_mdss)

drivers/gpu/drm/msm/msm_mdss.c

298

struct platform_device *pdev = to_platform_device(msm_mdss->dev);

drivers/gpu/drm/msm/msm_mdss.c

301

pm_runtime_suspend(msm_mdss->dev);

drivers/gpu/drm/msm/msm_mdss.c

302

pm_runtime_disable(msm_mdss->dev);

drivers/gpu/drm/msm/msm_mdss.c

303

irq_domain_remove(msm_mdss->irq_controller.domain);

drivers/gpu/drm/msm/msm_mdss.c

304

msm_mdss->irq_controller.domain = NULL;

drivers/gpu/drm/msm/msm_mdss.c

365

static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5)

drivers/gpu/drm/msm/msm_mdss.c

368

struct msm_mdss *msm_mdss;

drivers/gpu/drm/msm/msm_mdss.c

376

msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL);

drivers/gpu/drm/msm/msm_mdss.c

377

if (!msm_mdss)

drivers/gpu/drm/msm/msm_mdss.c

380

msm_mdss->mdss_data = qcom_ubwc_config_get_data();

drivers/gpu/drm/msm/msm_mdss.c

381

if (IS_ERR(msm_mdss->mdss_data))

drivers/gpu/drm/msm/msm_mdss.c

382

return ERR_CAST(msm_mdss->mdss_data);

drivers/gpu/drm/msm/msm_mdss.c

388

msm_mdss->reg_bus_bw = mdss_data->reg_bus_bw;

drivers/gpu/drm/msm/msm_mdss.c

390

msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss");

drivers/gpu/drm/msm/msm_mdss.c

391

if (IS_ERR(msm_mdss->mmio))

drivers/gpu/drm/msm/msm_mdss.c

392

return ERR_CAST(msm_mdss->mmio);

drivers/gpu/drm/msm/msm_mdss.c

394

dev_dbg(&pdev->dev, "mapped mdss address space @%p\n", msm_mdss->mmio);

drivers/gpu/drm/msm/msm_mdss.c

396

ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss);

drivers/gpu/drm/msm/msm_mdss.c

401

ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks);

drivers/gpu/drm/msm/msm_mdss.c

403

ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks);

drivers/gpu/drm/msm/msm_mdss.c

408

msm_mdss->num_clocks = ret;

drivers/gpu/drm/msm/msm_mdss.c

409

msm_mdss->is_mdp5 = is_mdp5;

drivers/gpu/drm/msm/msm_mdss.c

411

msm_mdss->dev = &pdev->dev;

drivers/gpu/drm/msm/msm_mdss.c

417

ret = _msm_mdss_irq_domain_add(msm_mdss);

drivers/gpu/drm/msm/msm_mdss.c

422

msm_mdss);

drivers/gpu/drm/msm/msm_mdss.c

426

return msm_mdss;

drivers/gpu/drm/msm/msm_mdss.c

431

struct msm_mdss *mdss = dev_get_drvdata(dev);

drivers/gpu/drm/msm/msm_mdss.c

440

struct msm_mdss *mdss = dev_get_drvdata(dev);

drivers/gpu/drm/msm/msm_mdss.c

471

struct msm_mdss *mdss;

drivers/gpu/drm/msm/msm_mdss.c

50

struct msm_mdss *msm_mdss)

drivers/gpu/drm/msm/msm_mdss.c

500

struct msm_mdss *mdss = platform_get_drvdata(pdev);

drivers/gpu/drm/msm/msm_mdss.c

60

msm_mdss->mdp_path[0] = path0;

drivers/gpu/drm/msm/msm_mdss.c

61

msm_mdss->num_mdp_paths = 1;

drivers/gpu/drm/msm/msm_mdss.c

65

msm_mdss->mdp_path[1] = path1;

drivers/gpu/drm/msm/msm_mdss.c

66

msm_mdss->num_mdp_paths++;

drivers/gpu/drm/msm/msm_mdss.c

71

msm_mdss->reg_bus_path = reg_bus_path;

drivers/gpu/drm/msm/msm_mdss.c

78

struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc);

drivers/gpu/drm/msm/msm_mdss.c

84

interrupts = readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_INTR_STATUS);

drivers/gpu/drm/msm/msm_mdss.c

90

rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain,

drivers/gpu/drm/msm/msm_mdss.c

93

dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n",