arch/x86/include/asm/div64.h

78

#define mul_u32_u32 mul_u32_u32

drivers/acpi/acpi_lpit.c

108

lpit_native->counter_frequency : mul_u32_u32(tsc_khz, 1000U);

drivers/clk/renesas/rzg2l-cpg.c

692

foutvco_rate = div_u64(mul_u32_u32(EXTAL_FREQ_IN_MEGA_HZ * MEGA,

drivers/clk/renesas/rzv2h-cpg.c

240

u64 fout_min_millihz = mul_u32_u32(limits->fout.min, MILLI);

drivers/clk/renesas/rzv2h-cpg.c

241

u64 fout_max_millihz = mul_u32_u32(limits->fout.max, MILLI);

drivers/clk/renesas/rzv2h-cpg.c

289

output_m = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(p.m, fref) * MILLI,

drivers/clk/renesas/rzv2h-cpg.c

292

output_k_range = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(fref, MILLI),

drivers/clk/renesas/rzv2h-cpg.c

327

fvco = mul_u32_u32(p.m * 65536 + p.k, fref);

drivers/clk/renesas/rzv2h-cpg.c

328

if (fvco < mul_u32_u32(limits->fvco.min, 65536) ||

drivers/clk/renesas/rzv2h-cpg.c

329

fvco > mul_u32_u32(limits->fvco.max, 65536))

drivers/clk/renesas/rzv2h-cpg.c

333

output = mul_u32_u32(p.m * 65536, RZ_V2H_OSC_CLK_IN_MEGA);

drivers/clk/renesas/rzv2h-cpg.c

453

rate_millihz = mul_u32_u32(req->rate, MILLI);

drivers/clk/renesas/rzv2h-cpg.c

575

rate_millihz = mul_u32_u32(req->rate, MILLI);

drivers/cpuidle/driver.c

193

s->exit_latency_ns = mul_u32_u32(s->exit_latency, NSEC_PER_USEC);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c

253

u64 cts = mul_u32_u32(pixel_clk, n);

drivers/gpu/drm/display/drm_dp_helper.c

4806

return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,

drivers/gpu/drm/display/drm_dp_helper.c

4865

return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate * 10 * max_lanes,

drivers/gpu/drm/display/drm_dp_mst_topology.c

3600

ret.full = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_rate * link_lane_count,

drivers/gpu/drm/display/drm_dp_mst_topology.c

4809

return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),

drivers/gpu/drm/drm_modes.c

1307

return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(num, 1000), den);

drivers/gpu/drm/drm_rect.c

65

tmp = mul_u32_u32(src, dst - *clip);

drivers/gpu/drm/i915/display/i9xx_wm.c

491

ret = mul_u32_u32(pixel_rate, cpp * latency);

drivers/gpu/drm/i915/display/intel_audio.c

485

hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk),

drivers/gpu/drm/i915/display/intel_audio.c

486

mul_u32_u32(link_clk, cdclk));

drivers/gpu/drm/i915/display/intel_audio.c

488

tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000),

drivers/gpu/drm/i915/display/intel_audio.c

489

mul_u32_u32(link_clk * lanes * 16, fec_coeff));

drivers/gpu/drm/i915/display/intel_audio.c

490

tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),

drivers/gpu/drm/i915/display/intel_audio.c

491

mul_u32_u32(64 * pixel_clk, 1000000));

drivers/gpu/drm/i915/display/intel_backlight.c

56

target_val = mul_u32_u32(source_val - source_min,

drivers/gpu/drm/i915/display/intel_cdclk.c

4260

return DIV_ROUND_UP_ULL(mul_u32_u32(pipe_mode->crtc_clock, prefill_lines_unadjusted),

drivers/gpu/drm/i915/display/intel_color.c

217

result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30;

drivers/gpu/drm/i915/display/intel_color.c

824

return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(val, (1 << 16) - 1),

drivers/gpu/drm/i915/display/intel_crtc.c

513

return DIV_ROUND_UP_ULL(mul_u32_u32(usecs, adjusted_mode->crtc_clock),

drivers/gpu/drm/i915/display/intel_crtc.c

524

return DIV_ROUND_UP_ULL(mul_u32_u32(scanlines, adjusted_mode->crtc_htotal * 1000),

drivers/gpu/drm/i915/display/intel_crtc.c

859

return DIV_ROUND_UP_ULL(mul_u32_u32(intel_crtc_bw_data_rate(crtc_state), 10), 512);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2188

tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2753

vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10);

drivers/gpu/drm/i915/display/intel_display.c

2517

*ret_m = div_u64(mul_u32_u32(m, *ret_n), n);

drivers/gpu/drm/i915/display/intel_display.c

4082

return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10),

drivers/gpu/drm/i915/display/intel_dp.c

479

return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead),

drivers/gpu/drm/i915/display/intel_dp.c

842

return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),

drivers/gpu/drm/i915/display/intel_dp_mst.c

172

return div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72,

drivers/gpu/drm/i915/display/intel_dp_mst.c

174

mul_u32_u32(adjusted_mode->crtc_clock, 1030000));

drivers/gpu/drm/i915/display/intel_dp_mst.c

210

m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n);

drivers/gpu/drm/i915/display/intel_dp_mst.c

485

return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(mode->htotal - mode->hdisplay,

drivers/gpu/drm/i915/display/intel_dpll.c

369

DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22);

drivers/gpu/drm/i915/display/intel_dpll.c

951

m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3115

tmp = mul_u32_u32(dco_khz, 47 * 32);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3119

tmp = mul_u32_u32(dco_khz, 1000);

drivers/gpu/drm/i915/display/intel_fb.c

1171

if (check_add_overflow(mul_u32_u32(height, fb->pitches[color_plane]),

drivers/gpu/drm/i915/display/intel_fb.c

1789

if (mul_u32_u32(max_size, tile_size) > obj->size) {

drivers/gpu/drm/i915/display/intel_fb.c

1792

mul_u32_u32(max_size, tile_size), obj->size);

drivers/gpu/drm/i915/display/intel_fixed.h

122

tmp = mul_u32_u32(val, mul.val);

drivers/gpu/drm/i915/display/intel_fixed.h

79

tmp = mul_u32_u32(val, mul.val);

drivers/gpu/drm/i915/display/intel_fixed.h

91

tmp = mul_u32_u32(val.val, mul.val);

drivers/gpu/drm/i915/display/intel_plane.c

221

return DIV_ROUND_UP_ULL(mul_u32_u32(rate, src_w * src_h),

drivers/gpu/drm/i915/display/intel_snps_phy.c

1944

return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +

drivers/gpu/drm/i915/display/intel_sprite.c

592

return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, num * src_w),

drivers/gpu/drm/i915/display/intel_sprite.c

955

return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, 10 * hscale),

drivers/gpu/drm/i915/display/intel_vblank.c

172

return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,

drivers/gpu/drm/i915/display/intel_vdsc.c

1088

num = mul_u32_u32(pixel_rate, (htotal + dsc_slice_bubbles));

drivers/gpu/drm/i915/display/intel_vrr.c

212

crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,

drivers/gpu/drm/i915/display/intel_vrr.c

214

vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n),

drivers/gpu/drm/i915/display/intel_vrr.c

216

adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m);

drivers/gpu/drm/i915/display/skl_prefill.c

24

return DIV_ROUND_UP_ULL(mul_u32_u32(pipe_mode->crtc_clock, usecs << 16),

drivers/gpu/drm/i915/display/skl_prefill.c

69

return DIV_ROUND_UP_ULL(mul_u32_u32(value, factor), 0x10000);

drivers/gpu/drm/i915/display/skl_watermark.c

2185

pixel_rate = DIV_ROUND_UP_ULL(mul_u32_u32(skl_scaler_max_total_scale(crtc_state),

drivers/gpu/drm/i915/display/skl_watermark.c

2190

width = DIV_ROUND_UP_ULL(mul_u32_u32(skl_scaler_max_hscale(crtc_state),

drivers/gpu/drm/i915/gem/i915_gem_create.c

202

args->size = mul_u32_u32(args->pitch, args->height);

drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c

186

div_u64(mul_u32_u32(gt->clock_period_ns, S32_MAX),

drivers/gpu/drm/i915/gt/intel_migrate.c

283

return upper_32_bits(mul_u32_u32(get_random_u32(), max));

drivers/gpu/drm/i915/gt/intel_region_lmem.c

236

mul_u32_u32(i915->params.lmem_size, SZ_1M));

drivers/gpu/drm/i915/gt/selftest_engine_cs.c

126

sum = mul_u32_u32(a[2], 2);

drivers/gpu/drm/i915/gt/selftest_migrate.c

885

div64_u64(mul_u32_u32(4 * sz,

drivers/gpu/drm/i915/gt/selftest_migrate.c

968

div64_u64(mul_u32_u32(4 * sz,

drivers/gpu/drm/i915/gvt/handlers.c

610

clock.vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock.m), clock.n << 22);

drivers/gpu/drm/i915/gvt/handlers.c

704

pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n);

drivers/gpu/drm/i915/gvt/handlers.c

708

new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal + 1, vtotal + 1));

drivers/gpu/drm/i915/i915_pmu.c

217

pmu->sample[gt_id][sample].cur += mul_u32_u32(val, mul);

drivers/gpu/drm/i915/selftests/i915_random.h

49

return upper_32_bits(mul_u32_u32(prandom_u32_state(state), ep_ro));

drivers/gpu/drm/i915/selftests/i915_request.c

1943

sum = mul_u32_u32(a[2], 2);

drivers/gpu/drm/i915/selftests/intel_memory_region.c

1282

div64_u64(mul_u32_u32(4 * size,

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c

570

*hsfreq_millihz = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(vclk_rate, bpp * MILLI),

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c

586

mode_freq_hz = mul_u32_u32(mode_freq, KILO);

drivers/gpu/drm/xe/xe_guc_submit.c

996

min_us = mul_u32_u32(delay_ms, 1000);

drivers/gpu/drm/xe/xe_hwmon.c

355

*value = mul_u32_u32(reg_val, SF_POWER) >> hwmon->scl_shift_power;

drivers/iio/adc/ad4030.c

465

gain = mul_u32_u32(gain_int, MICRO) + gain_frac;

drivers/iio/light/opt4060.c

737

uval = mul_u32_u32(int_time, pers);

drivers/iio/light/opt4060.c

749

uval = mul_u32_u32(val, MICRO) + val2;

drivers/iio/light/vcnl4000.c

619

data->al_scale = div_u64(mul_u32_u32(data->chip_spec->ulux_step,

drivers/iio/light/vcnl4000.c

710

val_c = mul_u32_u32((*data->chip_spec->als_it_times)[it][1],

drivers/iio/light/vcnl4000.c

722

u64 val_n = mul_u32_u32(val, MICRO) + val2;

drivers/iio/light/vcnl4000.c

733

if (val_n < mul_u32_u32(vcnl4040_als_persistence[i],

drivers/net/can/dev/bittiming.c

108

bt->tq = DIV_U64_ROUND_CLOSEST(mul_u32_u32(bt->brp, NSEC_PER_SEC),

drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c

4196

buflen = mul_u32_u32(dir_entries, entry_length);

drivers/net/ethernet/mellanox/mlx5/core/en_main.c

1003

u64 dma_offset = mul_u32_u32(i, rq->mpwqe.mtts_per_wqe) <<

drivers/ptp/ptp_netc.c

222

divisor = mul_u32_u32(2 * NSEC_PER_SEC, priv->oclk_prsc);

drivers/ptp/ptp_netc.c

223

pulse_width = div64_u64(mul_u32_u32(fiper, priv->clk_freq), divisor);

drivers/ptp/ptp_netc.c

286

return div_u64(mul_u32_u32(NSEC_PER_SEC, priv->oclk_prsc),

drivers/regulator/max5970-regulator.c

287

div_u64(mul_u32_u32(data->shunt_micro_ohms, data->lim_uA),

drivers/regulator/max5970-regulator.c

294

vthst = div_u64(mul_u32_u32(vthst, 120), 100);

drivers/regulator/max5970-regulator.c

304

val = div_u64(mul_u32_u32(0xFF, vthfst), data->irng);

fs/f2fs/dir.c

185

bidx += mul_u32_u32(dir_buckets(i, dir_level),

include/drm/drm_color_mgmt.h

46

return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(user_input, (1 << bit_precision) - 1),

include/linux/can/bittiming.h

276

return DIV_U64_ROUND_CLOSEST(mul_u32_u32(tqmin, NSEC_PER_SEC),

include/linux/math64.h

151

#ifndef mul_u32_u32

include/linux/math64.h

196

ret = mul_u32_u32(al, mul) >> shift;

include/linux/math64.h

198

ret += mul_u32_u32(ah, mul) << (32 - shift);

include/linux/math64.h

221

rl.ll = mul_u32_u32(a0.l.low, b0.l.low);

include/linux/math64.h

222

rm.ll = mul_u32_u32(a0.l.low, b0.l.high);

include/linux/math64.h

223

rn.ll = mul_u32_u32(a0.l.high, b0.l.low);

include/linux/math64.h

224

rh.ll = mul_u32_u32(a0.l.high, b0.l.high);

include/linux/math64.h

282

rl.ll = mul_u32_u32(u.l.low, mul);

include/linux/math64.h

283

rh.ll = mul_u32_u32(u.l.high, mul) + rl.l.high;

include/vdso/math64.h

36

#ifndef mul_u32_u32

include/vdso/math64.h

41

#define mul_u32_u32 mul_u32_u32

include/vdso/math64.h

49

ovf = __builtin_add_overflow(mul_u32_u32(al, mul), b, &ret);

include/vdso/math64.h

54

ret += mul_u32_u32(ah, mul) << (32 - shift);

kernel/sched/fair.c

275

fact = mul_u32_u32(fact, lw->inv_weight);

lib/dhry_1.c

289

return div_u64(mul_u32_u32(MSEC_PER_SEC, Number_Of_Runs), User_Time);

lib/math/div64.c

190

#define mul_add(a, b, c) add_u64_u32(mul_u32_u32(a, b), c)

net/ethtool/ioctl.c

2471

u64 count = mul_u32_u32(n, id.data);

net/sched/sch_dualpi2.c

683

u64 memlim = mul_u32_u32(limit, 2 * psched_mtu(qdisc_dev(sch)));

net/sched/sch_dualpi2.c

693

u64 ns = mul_u32_u32(us, NSEC_PER_USEC);

sound/soc/stm/stm32_i2s.c

352

dividend = mul_u32_u32(1000000, abs(max_rate - (ratio * rate)));

sound/soc/stm/stm32_sai_sub.c

372

dividend = mul_u32_u32(1000000, abs(max_rate - (ratio * rate)));

tools/include/linux/math64.h

54

ret = mul_u32_u32(al, b) >> shift;

tools/include/linux/math64.h

56

ret += mul_u32_u32(ah, b) << (32 - shift);