mtk_r32
val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
val = mtk_r32(ir, mtk_chkdata_reg(ir, i));
val = mtk_r32(ir, MTK_CONFIG_HIGH_REG) & ~MTK_OK_COUNT_MASK;
val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask);
val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask);
val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask);
val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask);
hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT);
hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT);
hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT);
hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT);
mtk_r32(mac->hw, MT7628_SDM_CS_ERR);
hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs);
stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs);
mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs);
mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs);
mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs);
mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs);
mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs);
mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs);
mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs);
mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs);
mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs);
mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs);
stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs);
mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs);
mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs);
mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs);
mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs);
stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs);
mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs);
dma = mtk_r32(eth, reg_map->qdma.drx_ptr);
dma = mtk_r32(eth, MT7628_TX_DTX_IDX0);
u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
mtk_r32(eth, reg_map->tx_irq_status),
mtk_r32(eth, reg_map->tx_irq_mask));
if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT)
mtk_r32(eth, reg_map->pdma.irq_status),
mtk_r32(eth, reg_map->pdma.irq_mask));
} while (mtk_r32(eth, reg_map->pdma.irq_status) &
val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
val = mtk_r32(eth, reg);
reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
u32 val = mtk_r32(eth, MTK_INT_STATUS2);
if (mtk_r32(eth, reg_map->pdma.irq_mask) &
if (mtk_r32(eth, reg_map->pdma.irq_status) &
if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {
if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT)
val = mtk_r32(eth, reg_map->qdma.glo_cfg);
val = mtk_r32(eth, MTK_GDMA_FWD_CFG(id));
u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
val = mtk_r32(eth, glo_cfg);
val = mtk_r32(eth, glo_cfg);
val = mtk_r32(eth, reg_map->pdma.delay_irq);
val = mtk_r32(eth, reg_map->pdma.delay_irq);
mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc);
val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204);
val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230);
oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) &&
!(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) &&
!(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16)));
qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234);
qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308);
gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0;
gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0;
gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1;
gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1;
gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24);
gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64);
return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK;
oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0));
cdm1_busy = !!(mtk_r32(eth, MTK_FE_CDM1_FSM) & GENMASK(31, 16));
adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) &&
!(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6));
val = mtk_r32(eth, MTK_FE_GLO_MISC);
val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i);
val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) | MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT);
val = mtk_r32(eth, MTK_MAC_MCR(i)) & ~MAC_MCR_FORCE_LINK;
return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK;
val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) & ~MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT);
mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id));
u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
return mtk_r32(eth, 0x0010) & mtk_get_ib1_ts_mask(eth);
l = (mtk_r32(hw, pf->index, pf->offset)
h = (mtk_r32(hw, pf->index, pf->offset + pf->next))
*value = (mtk_r32(hw, pf.index, pf.offset)
val = mtk_r32(pctl, i, reg);
val = mtk_r32(rtc, reg);
sec = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC));
min = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN));
hour = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU));
wday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW));
mday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM));
mon = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MON));
year = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA));
} while (sec != mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC)));
irq_sta = mtk_r32(hw, MTK_RTC_INT);
wkalrm->enabled = !!(mtk_r32(hw, MTK_RTC_AL_CTL) & RTC_AL_EN);
wkalrm->pending = !!(mtk_r32(hw, MTK_RTC_INT) & RTC_INT_AL_STA);