drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

116

mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IC_MASK, 0x1);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

117

mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IR_MASK, 0x1);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

118

mtk_phy_update_field(base + HDMI_CON2, RG_HDMITX_TX_POSDIV_MASK, pos_div);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

119

mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKSEL_MASK, 1);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

120

mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKDIV_MASK, 19);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

121

mtk_phy_update_field(base + HDMI_CON7, RG_HTPLL_DIVEN_MASK, 0x2);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

122

mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BP_MASK, 0xc);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

123

mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BC_MASK, 0x2);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

124

mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BR_MASK, 0x1);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

127

mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PRED_IBIAS_MASK, 0x3);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

129

mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_DRV_IMP_MASK, 0x28);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

130

mtk_phy_update_field(base + HDMI_CON4, RG_HDMITX_RESERVE_MASK, 0x28);

drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

131

mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_DRV_IBIAS_MASK, 0xa);

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

160

mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_PLL_PREDIV, pre_div);

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

166

mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV, div);

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

171

mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PLL_DIVEN, 0x2);

drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c

196

mtk_phy_update_field(base + HDMI_CON3, RG_HDMITX_DRV_IMP_EN, imp_en);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

100

mtk_phy_update_field(regs + HDMI_1_CFG_9, RG_HDMITX21_SLDO_VREF_SEL, 0x2);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

103

mtk_phy_update_field(regs + HDMI_1_CFG_6, RG_HDMITX21_INTR_CAL, 0x11);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

109

mtk_phy_update_field(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV, txposdiv_value);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

135

mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_POSDIV_DIV3_CTRL, div3_ctrl_value);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

136

mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_POSDIV, posdiv_vallue);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

156

mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_DIV_CTRL, div_ctrl_value);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

179

mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT3_2, reserve_3_2_value);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

182

mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT1_0, 0x2);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

187

mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_PREDIV, prediv_value);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

192

mtk_phy_update_field(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT13, reserve13_value);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

195

mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_FBKDIV_HIGH, fbkdiv_high);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

196

mtk_phy_update_field(regs + HDMI_1_PLL_CFG_3, RG_HDMITXPLL_FBKDIV_LOW, fbkdiv_low);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

205

mtk_phy_update_field(regs + HDMI_CTL_3, REG_HDMITXPLL_DIV, digital_div - 1);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

344

mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D0, data_channel_bias);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

345

mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D1, data_channel_bias);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

346

mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D2, data_channel_bias);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

347

mtk_phy_update_field(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_IBIAS_CLK, clk_channel_bias);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

350

mtk_phy_update_field(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_IMP_EN, impedance_en);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

351

mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D0_EN1, impedance);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

352

mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D1_EN1, impedance);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

353

mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D2_EN1, impedance);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

354

mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_CLK_EN1, impedance);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

39

mtk_phy_update_field(regs + HDMI20_CLK_CFG, REG_TXC_DIV, 3);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

63

mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_IC, 0x1);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

64

mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BR, 0x2);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

65

mtk_phy_update_field(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_IR, 0x2);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

70

mtk_phy_update_field(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_HREN, 0x1);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

71

mtk_phy_update_field(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_LVR_SEL, 0x1);

drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

98

mtk_phy_update_field(regs + HDMI_1_CFG_10, RG_HDMITX21_BIAS_PE_BG_VREF_SEL, 0x2);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

100

mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L0_CKMODE_EN, 0);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

101

mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L0_CKSEL, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

102

mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L1_CKMODE_EN, 0);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

103

mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L1_CKSEL, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

104

mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L2_CKMODE_EN, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

105

mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L2_CKSEL, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

107

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

109

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L0_CKSEL, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

110

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

112

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L1_CKSEL, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

113

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

115

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L2_CKSEL, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

118

mtk_phy_update_field(base + MIPI_RX_ANAA8_CSIXA, RG_CSIXA_CDPHY_L0_T0_BYTECK_INVERT, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

119

mtk_phy_update_field(base + MIPI_RX_ANAA8_CSIXA, RG_CSIXA_DPHY_L1_BYTECK_INVERT, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

120

mtk_phy_update_field(base + MIPI_RX_ANAA8_CSIXA, RG_CSIXA_CDPHY_L2_T1_BYTECK_INVERT, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

122

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANAA8_CSIXA,

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

124

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANAA8_CSIXA,

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

126

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANAA8_CSIXA,

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

138

mtk_phy_update_field(base + MIPI_RX_ANA24_CSIXA, RG_CSIXA_RESERVE, 0x40);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

139

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA24_CSIXA, RG_CSIXA_RESERVE, 0x40);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

140

mtk_phy_update_field(base + MIPI_RX_WRAPPER80_CSIXA, CSR_CSI_RST_MODE, 0);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

141

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_WRAPPER80_CSIXA, CSR_CSI_RST_MODE, 0);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

143

mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_CORE_EN, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

144

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_CORE_EN, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

146

mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_LPF_EN, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

147

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_LPF_EN, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

158

mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_CORE_EN, 0);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

159

mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_LPF_EN, 0);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

161

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_CORE_EN, 0);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

162

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_LPF_EN, 0);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

41

mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_IS, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

42

mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_BW, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

43

mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_IS, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

44

mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_BW, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

45

mtk_phy_update_field(base + MIPI_RX_ANA20_CSI0A, RG_CSI0A_L2_T1BC_EQ_IS, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

46

mtk_phy_update_field(base + MIPI_RX_ANA20_CSI0A, RG_CSI0A_L2_T1BC_EQ_BW, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

48

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_IS, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

49

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_BW, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

50

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_IS, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

51

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_BW, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

52

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA20_CSI0A, RG_CSI0A_L2_T1BC_EQ_IS, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

53

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA20_CSI0A, RG_CSI0A_L2_T1BC_EQ_BW, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

58

mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L0_EQ_IS, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

59

mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L0_EQ_BW, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

60

mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L1_EQ_IS, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

61

mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L1_EQ_BW, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

62

mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI1A_L2_EQ_IS, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

63

mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI1A_L2_EQ_BW, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

65

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L0_EQ_IS, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

66

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L0_EQ_BW, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

67

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L1_EQ_IS, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

68

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L1_EQ_BW, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

69

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, RG_CSI1A_L2_EQ_IS, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

70

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, RG_CSI1A_L2_EQ_BW, 1);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

84

mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSI0A_CPHY_EN, 0);

drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c

85

mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

207

mtk_phy_update_field(base + MIPITX_DSI_PLL_TOP,

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c

151

mtk_phy_update_field(base + MIPITX_VOLTAGE_SEL, RG_DSI_HSTX_LDO_REF_SEL,

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c

83

mtk_phy_update_field(base + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, txdiv0);

drivers/phy/mediatek/phy-mtk-pcie.c

119

mtk_phy_update_field(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG,

drivers/phy/mediatek/phy-mtk-pcie.c

92

mtk_phy_update_field(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_PMOS_SEL,

drivers/phy/mediatek/phy-mtk-pcie.c

95

mtk_phy_update_field(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_NMOS_SEL,

drivers/phy/mediatek/phy-mtk-pcie.c

98

mtk_phy_update_field(addr + PEXTP_ANA_RX_REG, EFUSE_LN_RX_SEL,

drivers/phy/mediatek/phy-mtk-tphy.c

1038

mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL4, RG_CDR_BIRLTD0_GEN1_MSK, 0x18);

drivers/phy/mediatek/phy-mtk-tphy.c

1040

mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL5, RG_CDR_BIRLTD0_GEN3_MSK, 0x06);

drivers/phy/mediatek/phy-mtk-tphy.c

1052

mtk_phy_update_field(phyd + PHYD_DESIGN_OPTION2, RG_LOCK_CNT_SEL_MSK, 0x02);

drivers/phy/mediatek/phy-mtk-tphy.c

1064

mtk_phy_update_field(phyd + ANA_RG_CTRL_SIGNAL1, RG_IDRV_0DB_GEN1_MSK, 0x20);

drivers/phy/mediatek/phy-mtk-tphy.c

1066

mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL1, RG_EQ_DLEQ_LFI_GEN1_MSK, 0x03);

drivers/phy/mediatek/phy-mtk-tphy.c

1165

mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL,

drivers/phy/mediatek/phy-mtk-tphy.c

1169

mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL,

drivers/phy/mediatek/phy-mtk-tphy.c

1173

mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL,

drivers/phy/mediatek/phy-mtk-tphy.c

1181

mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,

drivers/phy/mediatek/phy-mtk-tphy.c

1186

mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH,

drivers/phy/mediatek/phy-mtk-tphy.c

1190

mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP,

drivers/phy/mediatek/phy-mtk-tphy.c

1340

mtk_phy_update_field(u2_banks->com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,

drivers/phy/mediatek/phy-mtk-tphy.c

1347

mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL,

drivers/phy/mediatek/phy-mtk-tphy.c

1351

mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL,

drivers/phy/mediatek/phy-mtk-tphy.c

1355

mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR,

drivers/phy/mediatek/phy-mtk-tphy.c

465

mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL, val);

drivers/phy/mediatek/phy-mtk-tphy.c

469

mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL, val);

drivers/phy/mediatek/phy-mtk-tphy.c

474

mtk_phy_update_field(u2_banks->misc + U3P_MISC_REG1,

drivers/phy/mediatek/phy-mtk-tphy.c

479

mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, val);

drivers/phy/mediatek/phy-mtk-tphy.c

483

mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, val);

drivers/phy/mediatek/phy-mtk-tphy.c

487

mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP, val);

drivers/phy/mediatek/phy-mtk-tphy.c

581

mtk_phy_update_field(phyd + U3P_U3_PHYD_RSV,

drivers/phy/mediatek/phy-mtk-tphy.c

586

mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0,

drivers/phy/mediatek/phy-mtk-tphy.c

591

mtk_phy_update_field(phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL, val);

drivers/phy/mediatek/phy-mtk-tphy.c

596

mtk_phy_update_field(phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL, val);

drivers/phy/mediatek/phy-mtk-tphy.c

746

mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL,

drivers/phy/mediatek/phy-mtk-tphy.c

762

mtk_phy_update_field(phyd + U3P_U3_PHYD_TOP1, P3D_RG_PHY_MODE, 1);

drivers/phy/mediatek/phy-mtk-tphy.c

782

mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG0, P3A_RG_XTAL_EXT_EN_U3, 2);

drivers/phy/mediatek/phy-mtk-tphy.c

784

mtk_phy_update_field(phya + U3P_U3_PHYA_REG9, P3A_RG_RX_DAC_MUX, 4);

drivers/phy/mediatek/phy-mtk-tphy.c

786

mtk_phy_update_field(phya + U3P_U3_PHYA_REG6, P3A_RG_TX_EIDLE_CM, 0xe);

drivers/phy/mediatek/phy-mtk-tphy.c

793

mtk_phy_update_field(phyd + U3P_U3_PHYD_LFPS1, P3D_RG_FWAKE_TH, 0x34);

drivers/phy/mediatek/phy-mtk-tphy.c

795

mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET1, P3D_RG_RXDET_STB2_SET, 0x10);

drivers/phy/mediatek/phy-mtk-tphy.c

797

mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET2, P3D_RG_RXDET_STB2_SET_P3, 0x10);

drivers/phy/mediatek/phy-mtk-tphy.c

811

mtk_phy_update_field(com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV, 0);

drivers/phy/mediatek/phy-mtk-tphy.c

813

mtk_phy_update_field(com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW, 3);

drivers/phy/mediatek/phy-mtk-tphy.c

859

mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_SQTH, 2);

drivers/phy/mediatek/phy-mtk-tphy.c

966

mtk_phy_update_field(phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP, 0x4);

drivers/phy/mediatek/phy-mtk-tphy.c

968

mtk_phy_update_field(phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF, 0x1);

drivers/phy/mediatek/phy-mtk-tphy.c

971

mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG20, P3A_RG_PLL_DELTA1_PE2H, 0x3c);

drivers/phy/mediatek/phy-mtk-tphy.c

973

mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG25, P3A_RG_PLL_DELTA_PE2H, 0x36);

drivers/phy/mediatek/phy-mtk-tphy.c

985

mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG6, P3A_RG_PLL_IR_PE2H, 0x2);

drivers/phy/mediatek/phy-mtk-tphy.c

987

mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG7, P3A_RG_PLL_BP_PE2H, 0xa);

drivers/phy/mediatek/phy-mtk-tphy.c

990

mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET1,

drivers/phy/mediatek/phy-mtk-tphy.c

993

mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET2,

drivers/phy/mediatek/phy-mtk-xsphy.c

141

mtk_phy_update_field(pbase + XSP_U2FREQ_FMCR0, P2F_RG_CYCLECNT,

drivers/phy/mediatek/phy-mtk-xsphy.c

173

mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, calib_val);

drivers/phy/mediatek/phy-mtk-xsphy.c

290

mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_INTR_CAL,

drivers/phy/mediatek/phy-mtk-xsphy.c

294

mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL,

drivers/phy/mediatek/phy-mtk-xsphy.c

298

mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_VRT_SEL,

drivers/phy/mediatek/phy-mtk-xsphy.c

302

mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_TERM_SEL,

drivers/phy/mediatek/phy-mtk-xsphy.c

312

mtk_phy_update_field(xsphy->glb_base + SSPXTP_PHYA_GLB_00,

drivers/phy/mediatek/phy-mtk-xsphy.c

316

mtk_phy_update_field(pbase + SSPXTP_PHYA_LN_04,

drivers/phy/mediatek/phy-mtk-xsphy.c

320

mtk_phy_update_field(pbase + SSPXTP_PHYA_LN_14,