drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

185

cfg->mpll_cfg = dcn21_mpll_cfg_ref[0];

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

188

cfg->mpll_cfg = dcn21_mpll_cfg_ref[1];

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

191

cfg->mpll_cfg = dcn21_mpll_cfg_ref[2];

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

194

cfg->mpll_cfg = dcn21_mpll_cfg_ref[3];

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

53

static struct mpll_cfg dcn21_mpll_cfg_ref[] = {

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

225

cfg->mpll_cfg = dcn2_mpll_cfg[0];

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

228

cfg->mpll_cfg = dcn2_mpll_cfg[1];

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

231

cfg->mpll_cfg = dcn2_mpll_cfg[2];

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

234

cfg->mpll_cfg = dcn2_mpll_cfg[3];

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

58

static struct mpll_cfg dcn2_mpll_cfg[] = {

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h

292

struct mpll_cfg mpll_cfg;

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

1589

const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;

drivers/gpu/drm/imx/ipuv3/dw_hdmi-imx.c

167

.mpll_cfg = imx_mpll_cfg,

drivers/gpu/drm/imx/ipuv3/dw_hdmi-imx.c

174

.mpll_cfg = imx_mpll_cfg,

drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c

61

.mpll_cfg = ingenic_mpll_cfg,

drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

442

.mpll_cfg = rockchip_mpll_cfg,

drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

476

.mpll_cfg = rockchip_mpll_cfg,

drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

492

.mpll_cfg = rockchip_mpll_cfg,

drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

506

.mpll_cfg = rockchip_mpll_cfg,

drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h

154

const struct dw_hdmi_mpll_config *mpll_cfg;

drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c

584

plat_data->mpll_cfg = variant->mpll_cfg;

drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c

624

.mpll_cfg = sun50i_h6_mpll_cfg,

include/drm/bridge/dw_hdmi.h

170

const struct dw_hdmi_mpll_config *mpll_cfg;