mtk_m32
mtk_m32(eth, mask, set, reg);
mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0));
mtk_m32(eth, 0, MTK_XGMAC_FORCE_MODE(MTK_GMAC1_ID),
mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK,
mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE,
mtk_m32(mac->hw, MTK_XGMAC_FORCE_MODE(mac->id) |
mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL,
mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL);
mtk_m32(mac->hw,
mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE, XMAC_MCR_TRX_DISABLE,
mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), 0,
mtk_m32(mac->hw, XMAC_LOGIC_RST, 0, MTK_XMAC_LOGIC_RST(mac->id));
mtk_m32(mac->hw, XMAC_GLB_CNTCLR, XMAC_GLB_CNTCLR,
mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id),
mtk_m32(eth, MAC_MCR_EEE100M | MAC_MCR_EEE1G, 0, MTK_MAC_MCR(mac->id));
mtk_m32(eth, 0, MAC_MCR_EEE100M | MAC_MCR_EEE1G, MTK_MAC_MCR(mac->id));
mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3);
mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC);
u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);