drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2940

struct mpcc *mpcc_to_remove = params->mpc_remove_mpcc_params.mpcc_to_remove;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3477

struct mpcc *insert_above_mpcc = params->mpc_insert_plane_params.insert_above_mpcc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3877

struct mpc *mpc, struct mpc_tree *mpc_tree_params, struct mpcc *mpcc_to_remove)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4015

struct mpcc *insert_above_mpcc,

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c

62

static void mpc201_init_mpcc(struct mpcc *mpcc, int mpcc_inst)

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c

64

mpcc->mpcc_id = mpcc_inst;

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c

65

mpcc->dpp_id = 0xf;

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c

66

mpcc->mpcc_bot = NULL;

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c

67

mpcc->blnd_cfg.overlap_only = false;

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c

68

mpcc->blnd_cfg.global_alpha = 0xff;

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c

69

mpcc->blnd_cfg.global_gain = 0xff;

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c

70

mpcc->blnd_cfg.background_color_bpc = 4;

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c

71

mpcc->blnd_cfg.bottom_gain_mode = 0;

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c

72

mpcc->blnd_cfg.top_gain = 0x1f000;

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c

73

mpcc->blnd_cfg.bottom_inside_gain = 0x1f000;

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c

74

mpcc->blnd_cfg.bottom_outside_gain = 0x1f000;

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c

75

mpcc->sm_cfg.enable = false;

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c

76

mpcc->shared_bottom = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1494

struct mpcc *mpcc_to_remove = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2943

struct mpcc *new_mpcc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1521

new_pipe->update_flags.bits.mpcc = 1;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1598

new_pipe->update_flags.bits.mpcc = 1;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1761

if (pipe_ctx->update_flags.bits.mpcc

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2955

struct mpcc *new_mpcc;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3002

!pipe_ctx->update_flags.bits.mpcc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

387

struct mpcc *mpcc_to_remove = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

431

struct mpcc *new_mpcc;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

432

struct mpcc *remove_mpcc = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1492

phantom_pipe->update_flags.bits.mpcc = 1;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2903

new_pipe->update_flags.bits.mpcc = 1;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2979

new_pipe->update_flags.bits.mpcc = 1;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3194

struct mpcc *mpcc_to_remove = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3762

if (pipe_ctx->update_flags.bits.mpcc ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3883

struct mpcc *new_mpcc;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3928

!pipe_ctx->update_flags.bits.mpcc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

304

struct mpcc *new_mpcc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

352

!pipe_ctx->update_flags.bits.mpcc) {

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2048

struct mpc *mpc, struct mpc_tree *mpc_tree_params, struct mpcc *mpcc_to_remove);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2296

struct mpcc *insert_above_mpcc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

435

struct mpcc *insert_above_mpcc;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

443

struct mpcc *mpcc_to_remove;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

421

uint32_t mpcc : 1;

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

286

struct mpcc *mpcc_bot;

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

320

struct mpcc *opp_list;

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

327

struct mpcc mpcc_array[MAX_MPCC];

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

425

struct mpcc* (*insert_plane)(

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

430

struct mpcc *insert_above_mpcc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

452

struct mpcc *mpcc);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

546

struct mpcc* (*insert_plane_to_secondary)(

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

551

struct mpcc *insert_above_mpcc,

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

573

struct mpcc *mpcc);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

589

struct mpcc* (*get_mpcc_for_dpp_from_secondary)(

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

607

struct mpcc* (*get_mpcc_for_dpp)(

drivers/gpu/drm/amd/display/dc/inc/hw/opp.h

232

int mpcc[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

119

struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

125

struct mpcc *mpc1_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

127

struct mpcc *tmp_mpcc = tree->opp_list;

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

177

struct mpcc *mpc1_insert_plane(

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

182

struct mpcc *insert_above_mpcc,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

187

struct mpcc *new_mpcc = NULL;

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

195

struct mpcc *temp_mpcc = tree->opp_list;

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

231

struct mpcc *temp_mpcc = tree->opp_list;

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

272

struct mpcc *mpcc_to_remove)

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

292

struct mpcc *temp_mpcc = tree->opp_list;

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

334

static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst)

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

336

mpcc->mpcc_id = mpcc_inst;

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

337

mpcc->dpp_id = 0xf;

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

338

mpcc->mpcc_bot = NULL;

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

339

mpcc->blnd_cfg.overlap_only = false;

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

340

mpcc->blnd_cfg.global_alpha = 0xff;

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

341

mpcc->blnd_cfg.global_gain = 0xff;

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

342

mpcc->sm_cfg.enable = false;

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

403

struct mpcc *mpcc;

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

419

mpcc = mpc1_get_mpcc(mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

420

mpcc->dpp_id = top_sel;

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

424

tree->opp_list = mpcc;

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

430

struct mpcc *mpcc_bottom = mpc1_get_mpcc(mpc, bot_mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

432

mpcc->mpcc_bot = mpcc_bottom;

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

45

struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

82

struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

91

mpcc->blnd_cfg = *blnd_cfg;

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

141

struct mpcc *mpc1_insert_plane(

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

146

struct mpcc *insert_above_mpcc,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

153

struct mpcc *mpcc);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

184

struct mpcc *mpc1_get_mpcc(

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.h

188

struct mpcc *mpc1_get_mpcc_for_dpp(

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

507

static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst)

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

509

mpcc->mpcc_id = mpcc_inst;

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

510

mpcc->dpp_id = 0xf;

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

511

mpcc->mpcc_bot = NULL;

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

512

mpcc->blnd_cfg.overlap_only = false;

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

513

mpcc->blnd_cfg.global_alpha = 0xff;

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

514

mpcc->blnd_cfg.global_gain = 0xff;

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

515

mpcc->blnd_cfg.background_color_bpc = 4;

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

516

mpcc->blnd_cfg.bottom_gain_mode = 0;

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

517

mpcc->blnd_cfg.top_gain = 0x1f000;

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

518

mpcc->blnd_cfg.bottom_inside_gain = 0x1f000;

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

519

mpcc->blnd_cfg.bottom_outside_gain = 0x1f000;

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

520

mpcc->sm_cfg.enable = false;

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

523

static struct mpcc *mpc2_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id)

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

525

struct mpcc *tmp_mpcc = tree->opp_list;

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

53

struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

68

mpcc->blnd_cfg = *blnd_cfg;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1049

void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1051

mpcc->mpcc_id = mpcc_inst;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1052

mpcc->dpp_id = 0xf;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1053

mpcc->mpcc_bot = NULL;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1054

mpcc->blnd_cfg.overlap_only = false;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1055

mpcc->blnd_cfg.global_alpha = 0xff;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1056

mpcc->blnd_cfg.global_gain = 0xff;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1057

mpcc->blnd_cfg.background_color_bpc = 4;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1058

mpcc->blnd_cfg.bottom_gain_mode = 0;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1059

mpcc->blnd_cfg.top_gain = 0x1f000;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1060

mpcc->blnd_cfg.bottom_inside_gain = 0x1f000;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1061

mpcc->blnd_cfg.bottom_outside_gain = 0x1f000;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1062

mpcc->sm_cfg.enable = false;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1063

mpcc->shared_bottom = false;

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1104

void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

23

void mpc42_init_mpcc(struct mpcc *mpcc, int mpcc_inst)

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

25

mpcc->mpcc_id = mpcc_inst;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

26

mpcc->dpp_id = 0xf;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

27

mpcc->mpcc_bot = NULL;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

28

mpcc->blnd_cfg.overlap_only = false;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

29

mpcc->blnd_cfg.global_alpha = 0xfff;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

30

mpcc->blnd_cfg.global_gain = 0xfff;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

31

mpcc->blnd_cfg.background_color_bpc = 4;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

32

mpcc->blnd_cfg.bottom_gain_mode = 0;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

33

mpcc->blnd_cfg.top_gain = 0x1f000;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

34

mpcc->blnd_cfg.bottom_inside_gain = 0x1f000;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

35

mpcc->blnd_cfg.bottom_outside_gain = 0x1f000;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

36

mpcc->sm_cfg.enable = false;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

37

mpcc->shared_bottom = false;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

47

struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c

63

mpcc->blnd_cfg = *blnd_cfg;

drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h

885

void mpc42_init_mpcc(struct mpcc *mpcc, int mpcc_inst);