mpc8xxx_spi
int fsl_spi_cpm_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t)
void fsl_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
void fsl_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
static unsigned long fsl_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
int fsl_spi_cpm_init(struct mpc8xxx_spi *mspi)
void fsl_spi_cpm_free(struct mpc8xxx_spi *mspi)
void fsl_spi_cpm_reinit_txrx(struct mpc8xxx_spi *mspi)
static void fsl_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
extern void fsl_spi_cpm_reinit_txrx(struct mpc8xxx_spi *mspi);
extern int fsl_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
extern void fsl_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi);
extern void fsl_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events);
extern int fsl_spi_cpm_init(struct mpc8xxx_spi *mspi);
extern void fsl_spi_cpm_free(struct mpc8xxx_spi *mspi);
static inline void fsl_spi_cpm_reinit_txrx(struct mpc8xxx_spi *mspi) { }
static inline int fsl_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
static inline void fsl_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi) { }
static inline void fsl_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events) { }
static inline int fsl_spi_cpm_init(struct mpc8xxx_spi *mspi) { return 0; }
static inline void fsl_spi_cpm_free(struct mpc8xxx_spi *mspi) { }
mpc8xxx_spi->spibrg = pdata->sysclk;
mpc8xxx_spi->irq = irq;
mpc8xxx_spi->rx_shift = 0;
mpc8xxx_spi->tx_shift = 0;
init_completion(&mpc8xxx_spi->done);
void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
type *rx = mpc8xxx_spi->rx; \
*rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \
mpc8xxx_spi->rx = rx; \
u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
const type *tx = mpc8xxx_spi->tx; \
data = *tx++ << mpc8xxx_spi->tx_shift; \
mpc8xxx_spi->tx = tx; \
struct mpc8xxx_spi *mpc8xxx_spi;
mpc8xxx_spi = spi_controller_get_devdata(ctlr);
mpc8xxx_spi->dev = dev;
mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
mpc8xxx_spi->flags = pdata->flags;
extern void mpc8xxx_spi_rx_buf_u8(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
extern void mpc8xxx_spi_rx_buf_u16(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
extern void mpc8xxx_spi_rx_buf_u32(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
u32(*get_tx) (struct mpc8xxx_spi *);
void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
u32 (*get_tx) (struct mpc8xxx_spi *);
extern u32 mpc8xxx_spi_tx_buf_u8(struct mpc8xxx_spi *mpc8xxx_spi);
extern u32 mpc8xxx_spi_tx_buf_u16(struct mpc8xxx_spi *mpc8xxx_spi);
extern u32 mpc8xxx_spi_tx_buf_u32(struct mpc8xxx_spi *mpc8xxx_spi);
struct mpc8xxx_spi *mpc8xxx_spi,
if (mpc8xxx_spi->set_shifts)
mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
mpc8xxx_spi->rx_shift = cs->rx_shift;
mpc8xxx_spi->tx_shift = cs->tx_shift;
mpc8xxx_spi->get_rx = cs->get_rx;
mpc8xxx_spi->get_tx = cs->get_tx;
struct mpc8xxx_spi *mpc8xxx_spi;
mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
mspi_apply_cpu_mode_quirks(cs, spi, mpc8xxx_spi, bits_per_word);
if ((mpc8xxx_spi->spibrg / hz) > 64) {
pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024);
pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
reg_base = mpc8xxx_spi->reg_base;
mpc8xxx_spi->tx = t->tx_buf;
mpc8xxx_spi->rx = t->rx_buf;
reinit_completion(&mpc8xxx_spi->done);
if (mpc8xxx_spi->flags & SPI_CPM_MODE)
ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t);
ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
wait_for_completion(&mpc8xxx_spi->done);
if (mpc8xxx_spi->flags & SPI_CPM_MODE)
fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
return mpc8xxx_spi->count;
struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(ctlr);
if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
!(t->len & 1) && (mpc8xxx_spi->flags & SPI_CPM1))
struct mpc8xxx_spi *mpc8xxx_spi;
mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
reg_base = mpc8xxx_spi->reg_base;
static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
struct mpc8xxx_spi *mspi = context_data;
struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
if (cs < mpc8xxx_spi->native_chipselects) {
struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(host);
struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
mpc8xxx_spi->max_bits_per_word = mbits + 1;
mpc8xxx_spi->native_chipselects = 0;
mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
host->num_chipselect = mpc8xxx_spi->native_chipselects;
struct mpc8xxx_spi *mpc8xxx_spi;
host = devm_spi_alloc_host(dev, sizeof(struct mpc8xxx_spi));
mpc8xxx_spi = spi_controller_get_devdata(host);
mpc8xxx_spi->max_bits_per_word = 32;
mpc8xxx_spi->type = fsl_spi_get_type(dev);
ret = fsl_spi_cpm_init(mpc8xxx_spi);
mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
if (IS_ERR(mpc8xxx_spi->reg_base)) {
ret = PTR_ERR(mpc8xxx_spi->reg_base);
if (mpc8xxx_spi->type == TYPE_GRLIB)
if (mpc8xxx_spi->flags & SPI_CPM_MODE)
SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
if (mpc8xxx_spi->set_shifts)
mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
&mpc8xxx_spi->tx_shift, 8, 1);
ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
0, "fsl_spi", mpc8xxx_spi);
reg_base = mpc8xxx_spi->reg_base;
if (mpc8xxx_spi->max_bits_per_word < 8) {
regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
fsl_spi_cpm_free(mpc8xxx_spi);
struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(host);
fsl_spi_cpm_free(mpc8xxx_spi);
struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(host);
fsl_spi_cpm_free(mpc8xxx_spi);
struct mpc8xxx_spi *mspi = spi_controller_get_devdata(spi->controller);