drivers/gpu/drm/mediatek/mtk_ddp_comp.c

197

mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

199

mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

201

mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_ddp_comp.c

210

mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);

drivers/gpu/drm/mediatek/mtk_ddp_comp.h

362

void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

116

mtk_ddp_write_mask(cmdq_pkt, BUFFER_MODE,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

120

mtk_ddp_write_mask(cmdq_pkt, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

124

mtk_ddp_write_mask(cmdq_pkt, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

188

mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_merge.c

190

mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

291

mtk_ddp_write_mask(cmdq_pkt, enabled ? OVL_LAYER_AFBC_EN(idx) : 0,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

308

mtk_ddp_write_mask(cmdq_pkt, OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx),

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

389

mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs,

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

398

mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

193

mtk_ddp_write_mask(cmdq_pkt, width, &rdma->cmdq_reg, rdma->regs,

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

195

mtk_ddp_write_mask(cmdq_pkt, height, &rdma->cmdq_reg, rdma->regs,

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

273

mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, &rdma->cmdq_reg, rdma->regs,

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

276

mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB,

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

280

mtk_ddp_write_mask(cmdq_pkt, 0, &rdma->cmdq_reg, rdma->regs,

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

290

mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, &rdma->cmdq_reg, rdma->regs,

drivers/gpu/drm/mediatek/mtk_ethdr.c

210

mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,

drivers/gpu/drm/mediatek/mtk_ethdr.c

258

mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

153

mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | VAL_PRE_ULTRA_EN_ENABLE << 16 |

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

165

mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

173

mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

190

mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

192

mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

196

mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB, &priv->cmdq_reg,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

199

mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

202

mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

205

mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

208

mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_COMP_CON,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

210

mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

212

mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

215

mtk_ddp_write_mask(cmdq_pkt, rdma_color_convert(cfg->color_encoding) << 23,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

218

mtk_ddp_write_mask(cmdq_pkt, csc_enable << 16, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

223

mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

225

mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

227

mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

229

mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,

drivers/gpu/drm/mediatek/mtk_mdp_rdma.c

231

mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,