arch/powerpc/boot/4xx.c

283

mtdcr(DCRN_MAL0_CFG, MAL_RESET);

arch/powerpc/boot/4xx.c

299

mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i));

arch/powerpc/boot/dcr.h

171

mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \

arch/powerpc/boot/dcr.h

174

mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \

arch/powerpc/boot/dcr.h

175

mtdcr(DCRN_SDR0_CONFIG_DATA, data); })

arch/powerpc/boot/dcr.h

189

mtdcr(DCRN_CPR0_CFGADDR, offset); \

arch/powerpc/boot/dcr.h

192

mtdcr(DCRN_CPR0_CFGADDR, offset); \

arch/powerpc/boot/dcr.h

193

mtdcr(DCRN_CPR0_CFGDATA, data); })

arch/powerpc/boot/dcr.h

29

mtdcr(DCRN_SDRAM0_CFGADDR, offset); \

arch/powerpc/boot/dcr.h

32

mtdcr(DCRN_SDRAM0_CFGADDR, offset); \

arch/powerpc/boot/dcr.h

33

mtdcr(DCRN_SDRAM0_CFGDATA, data); })

arch/powerpc/include/asm/dcr-native.h

30

#define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value)

arch/powerpc/platforms/44x/fsp2.c

250

mtdcr(DCRN_PLB6_BASE, val);

arch/powerpc/platforms/44x/fsp2.c

251

mtdcr(DCRN_PLB6_HD, 0xffff0000);

arch/powerpc/platforms/44x/fsp2.c

252

mtdcr(DCRN_PLB6_SHD, 0xffff0000);

arch/powerpc/platforms/44x/fsp2.c

296

mtdcr(DCRN_CONF_EIR_RS, 0x80000000);

arch/powerpc/platforms/44x/fsp2.h

249

mtdcr(DCRN_CMU_ADDR, reg); \

arch/powerpc/platforms/44x/fsp2.h

250

mtdcr(DCRN_CMU_DATA, data); \

arch/powerpc/platforms/44x/fsp2.h

255

mtdcr(DCRN_CMU_ADDR, reg); \

arch/powerpc/platforms/44x/fsp2.h

261

mtdcr(DCRN_L2CDCRAI, reg); \

arch/powerpc/platforms/44x/fsp2.h

262

mtdcr(DCRN_L2CDCRDI, data); \

arch/powerpc/platforms/44x/fsp2.h

267

mtdcr(DCRN_L2CDCRAI, reg); \

arch/powerpc/platforms/44x/soc.c

126

mtdcr(dcrbase_isram + DCRN_SRAM0_DPC,

arch/powerpc/platforms/44x/soc.c

128

mtdcr(dcrbase_isram + DCRN_SRAM0_SB0CR,

arch/powerpc/platforms/44x/soc.c

130

mtdcr(dcrbase_isram + DCRN_SRAM0_SB1CR,

arch/powerpc/platforms/44x/soc.c

132

mtdcr(dcrbase_isram + DCRN_SRAM0_SB2CR,

arch/powerpc/platforms/44x/soc.c

134

mtdcr(dcrbase_isram + DCRN_SRAM0_SB3CR,

arch/powerpc/platforms/44x/soc.c

141

mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);

arch/powerpc/platforms/44x/soc.c

143

mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);

arch/powerpc/platforms/44x/soc.c

146

mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_HCC);

arch/powerpc/platforms/44x/soc.c

151

mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);

arch/powerpc/platforms/44x/soc.c

157

mtdcr(dcrbase_l2c + DCRN_L2C0_SNP0, r);

arch/powerpc/platforms/44x/soc.c

162

mtdcr(dcrbase_l2c + DCRN_L2C0_SNP1, r);

arch/powerpc/platforms/44x/soc.c

178

mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);

arch/powerpc/platforms/44x/soc.c

35

mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, addr);

arch/powerpc/platforms/44x/soc.c

36

mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_DIAG);

arch/powerpc/platforms/44x/soc.c

62

mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);

arch/powerpc/platforms/44x/soc.c

63

mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);

arch/powerpc/platforms/44x/uic.c

106

mtdcr(uic->dcrbase + UIC_ER, er);

arch/powerpc/platforms/44x/uic.c

116

mtdcr(uic->dcrbase + UIC_SR, sr);

arch/powerpc/platforms/44x/uic.c

157

mtdcr(uic->dcrbase + UIC_PR, pr);

arch/powerpc/platforms/44x/uic.c

158

mtdcr(uic->dcrbase + UIC_TR, tr);

arch/powerpc/platforms/44x/uic.c

159

mtdcr(uic->dcrbase + UIC_SR, ~mask);

arch/powerpc/platforms/44x/uic.c

264

mtdcr(uic->dcrbase + UIC_ER, 0);

arch/powerpc/platforms/44x/uic.c

265

mtdcr(uic->dcrbase + UIC_CR, 0);

arch/powerpc/platforms/44x/uic.c

266

mtdcr(uic->dcrbase + UIC_TR, 0);

arch/powerpc/platforms/44x/uic.c

268

mtdcr(uic->dcrbase + UIC_SR, 0xffffffff);

arch/powerpc/platforms/44x/uic.c

63

mtdcr(uic->dcrbase + UIC_SR, sr);

arch/powerpc/platforms/44x/uic.c

66

mtdcr(uic->dcrbase + UIC_ER, er);

arch/powerpc/platforms/44x/uic.c

80

mtdcr(uic->dcrbase + UIC_ER, er);

arch/powerpc/platforms/44x/uic.c

91

mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src));