mtcr
mtcr r6, psr
mtcr sp, usp
mtcr sp, ss0
mtcr r13, ss2
mtcr a0, epc
mtcr a0, epsr
mtcr a0, ss1
mtcr("cr<1, 2>", tmp1);
mtcr("cr<2, 2>", tmp2);
mtcr("cr<1, 2>", regx);
mtcr("cr<2, 2>", regx);
mtcr("cr<8, 15>", 0x02000000);
mtcr("cr<0, 15>", value);
mtcr("cr<6, 15>", value);
mtcr("cr<4, 15>", value);
mtcr("cr<30, 15>", value);
mtcr("cr<31, 15>", value);
mtcr("cr<8, 15>", 0x80000000);
mtcr("cr<8, 15>", 0x40000000);
mtcr("cr<8, 15>", 0x04000000);
mtcr a0, cr14
mtcr lr, cr14
mtcr \rx, cr<4, 15>
mtcr \rx, cr<8, 15>
mtcr r6, psr
mtcr r6, cr17
mtcr r6, cr<8, 15> /* Set MCIR */
mtcr r6, cr<6, 15> /* Set MPR with 4K page size */
mtcr r6, cr<4, 15> /* Set MEH */
mtcr r8, cr<2, 15> /* Set MEL0 */
mtcr r8, cr<3, 15> /* Set MEL1 */
mtcr r8, cr<8, 15> /* Set MCIR to write TLB */
mtcr r6, MSA_SET /* Set MSA */
mtcr r6, MSA_CLR /* Clr MSA */
mtcr r6, cr18
mtcr a0, epc
mtcr a0, epsr
mtcr a0, usp
mtcr a0, ss0
mtcr a0, cr14
static inline void init_fpu(void) { mtcr("cr<1, 2>", 0); }
mtcr("psr", flags);
mtcr("cr17", 0x22);
mtcr("cr<29, 0>", mask);
mtcr("cr31", secondary_hint);
mtcr("cr<21, 1>", secondary_hint2);
mtcr("cr18", secondary_ccr);
mtcr("vbr", vec_base);
mtcr("vbr", vec_base);
mtcr("cr<28, 0>", virt_to_phys(vec_base));
mtcr("cr22", i);
mtcr("cr17", val);
mtcr("cr17", value | CACHE_CLR);
mtcr("cr24", value | CACHE_CLR);
mtcr("cr24", val);
mtcr("cr17", INS_CACHE|CACHE_INV);
mtcr("cr22", i);
mtcr("cr17", val);
mtcr r14; \
__u32 mtcr : 1;
new.mtcr = val;
topo = kvm->arch.sca->utility.mtcr;
mtcr(PTIM_LVR, delta);
mtcr(PTIM_CTLR, 0);
mtcr(PTIM_CTLR, 1);
mtcr(PTIM_CTLR, 0);
mtcr(PTIM_TSR, 0);