mt76_rmw
#define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val)
#define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0)
mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
mt76_rmw(dev, MT_WF_RMAC_RMCR,
mt76_rmw(dev, MT_DMA_VCFR0, BIT(0), BIT(13));
mt76_rmw(dev, MT_DMA_TMCFR0, BIT(0) | BIT(1), BIT(13));
mt76_rmw(dev, MT_WF_RMAC_MAXMINLEN, 0xffffff, 0x19000);
mt76_rmw(dev, addr + 3 * 4, MT_WTBL1_W3_POWER_SAVE,
mt76_rmw(dev, addr + (15 * 4), tid_mask, tid_val);
mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
mt76_rmw(dev, MT_SCH_4, MT_SCH_4_FORCE_QID,
mt76_rmw(dev, reg + MT_DMASHDL_PKT_MAX_SIZE,
mt76_rmw(dev, MT_DMA_SHDL(MT_DMASHDL_PKT_MAX_SIZE),
mt76_rmw(dev, MT_DMA_RCFR0(chain), mask, set);
mt76_rmw(dev, MT_TMAC_CTCR0,
mt76_rmw(dev, MT_AGG_SCR, MT_AGG_SCR_NLNAV_MID_PTEC_DIS,
mt76_rmw(dev, MT_TMAC_TRCR(chain),
mt76_rmw(dev, addr, MT_LPON_TCR_MODE, MT_LPON_TCR_READ); /* TSF read */
mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE,
mt76_rmw(dev, MT7663_WF_PHY_MIN_PRI_PWR(ext_phy),
mt76_rmw(dev, MT7663_WF_PHY_RXTD_CCK_PD(ext_phy),
mt76_rmw(dev, MT_WF_PHY_MIN_PRI_PWR(ext_phy),
mt76_rmw(dev, MT_WF_PHY_RXTD_CCK_PD(ext_phy),
mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
mt76_rmw(dev, reg, MT_LPON_TCR_MODE, MT_LPON_TCR_READ);
mt76_rmw(dev, reg, MT_LPON_TCR_MODE, MT_LPON_TCR_WRITE);
mt76_rmw(dev, reg, MT_LPON_TCR_MODE, MT_LPON_TCR_ADJUST);
mt76_rmw(dev, addr, MT_LPON_TCR_MODE, MT_LPON_TCR_READ); /* TSF read */
mt76_rmw(dev, MT_DMA_SHDL(MT_DMASHDL_PKT_MAX_SIZE),
mt76_rmw(dev, MT_UDMA_WLCFG_0, MT_WL_RX_AGG_LMT | MT_WL_RX_AGG_TO,
mt76_rmw(dev, MT_WMM_CTRL, 0x3ff, 0x201);
mt76_rmw(dev, MT_CMB_CTRL, GENMASK(15, 0), ee_ant);
mt76_rmw(dev, MT_CSR_EE_CFG1, GENMASK(15, 0), ee_cfg1);
mt76_rmw(dev, MT_EXT_CCA_CFG,
mt76_rmw(dev, MT_US_CYC_CFG, MT_US_CYC_CNT, 0x1e);
mt76_rmw(dev, MT_BBP(AGC, 2), GENMASK(15, 0),
mt76_rmw(dev, MT_CCK_PROT_CFG,
mt76_rmw(dev, MT_OFDM_PROT_CFG,
mt76_rmw(dev, MT_MCU_COM_REG0, BIT(31), 0);
mt76_rmw(dev, MT_EXT_CCA_CFG,
mt76_rmw(dev, MT_US_CYC_CFG, MT_US_CYC_CNT, 0x1e);
mt76_rmw(dev, MT_EXT_CCA_CFG,
mt76_rmw(dev, MT_WFDMA0_EXT0_CFG, MT_WFDMA0_EXT0_RXWB_KEEP,
mt76_rmw(dev, MT_WFDMA0_EXT0_CFG, MT_WFDMA0_EXT0_RXWB_KEEP,
mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set);
mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set);
mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set);
mt76_rmw(dev, MT_WTBLOFF_TOP_RSCR(band), mask, set);
mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0,
mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
mt76_rmw(dev, MT_LPON_TCR(band, n), MT_LPON_TCR_SW_MODE,
mt76_rmw(dev, MT_LPON_TCR_MT7916(band, n), MT_LPON_TCR_SW_MODE,
mt76_rmw(dev, MT_LPON_TCR(band, n), MT_LPON_TCR_SW_MODE,
mt76_rmw(dev, MT_LPON_TCR_MT7916(band, n), MT_LPON_TCR_SW_MODE,
mt76_rmw(dev, MT_LPON_TCR(band, n), MT_LPON_TCR_SW_MODE,
mt76_rmw(dev, MT_LPON_TCR_MT7916(band, n), MT_LPON_TCR_SW_MODE,
mt76_rmw(dev, MT_MCU_BUS_TIMEOUT, mask, val);
mt76_rmw(dev, MT_MCU_BUS_DBG_TIMEOUT, mask, val);
mt76_rmw(dev, MT_AFE_DIG_EN_01(idx),
mt76_rmw(dev, MT_AFE_DIG_EN_03(idx),
mt76_rmw(dev, MT_AFE_PLL_STB_TIME(band),
mt76_rmw(dev, MT_AFE_DIG_EN_02(band),
mt76_rmw(dev, MT_AFE_DIG_TOP_01(band),
mt76_rmw(dev, MT_CONN_INFRA_OSC_RC_EN,
mt76_rmw(dev, MT_CONN_INFRA_OSC_CTRL,
mt76_rmw(dev, MT_TOP_WFSYS_PWR,
mt76_rmw(dev, MT_TOP_CONN_INFRA_WAKEUP,
mt76_rmw(dev, MT_TOP_CONN_INFRA_WAKEUP,
mt76_rmw(dev, MT_TOP_WFSYS_PWR, mask,
mt76_rmw(dev, MT_CONN_INFRA_WF_SLP_PROT,
mt76_rmw(dev, MT_AGG_MRCR(band), MT_AGG_MRCR_RTS_FAIL_LIMIT |
mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
mt76_rmw(dev, MT_UWFDMA0_GLO_CFG_EXT1, BIT(28), BIT(28));
mt76_rmw(dev, MT_WTBLOFF_TOP_RSCR(band), mask, set);
mt76_rmw(dev, MT_UWFDMA0_TX_RING_EXT_CTRL((_idx_)), \
mt76_rmw(dev, MT_DMASHDL_REFILL, MT_DMASHDL_REFILL_MASK, 0xffe00000);
mt76_rmw(dev, MT_DMASHDL_PKT_MAX_SIZE,
mt76_rmw(dev, MT_WFDMA_AXI_R2A_CTRL,
mt76_rmw(dev, WF_WFDMA0_GLO_CFG_EXT0 + hif1_ofs,
mt76_rmw(dev, MT_WFDMA_AXI_R2A_CTRL2,
mt76_rmw(dev, WF_WFDMA0_GLO_CFG_EXT0 + hif1_ofs,
mt76_rmw(dev, MT_WFDMA_AXI_R2A_CTRL2,
mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND0), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0);
mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND1), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0);
mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set);
mt76_rmw(dev, MT_WTBLOFF_RSCR(band), mask, set);
mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
mt76_rmw(dev, MT_LPON_TCR(phy->mt76->band_idx, n), MT_LPON_TCR_SW_MODE,
mt76_rmw(dev, MT_LPON_TCR(phy->mt76->band_idx, n), MT_LPON_TCR_SW_MODE,
mt76_rmw(dev, MT_LPON_TCR(phy->mt76->band_idx, n), MT_LPON_TCR_SW_MODE,
mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
return mt76_rmw(dev, offset, 0, val);
return mt76_rmw(dev, offset, val, 0);
mt76_rmw(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP,