drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

175

tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

177

WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

308

WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

494

tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

496

WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

507

tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

509

WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

179

WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

334

tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

336

WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

350

tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

352

WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

382

orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

385

WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

388

WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

197

data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

199

WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

221

data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

223

WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

560

WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

642

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), 0x3F, ~0x3F);