drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

171

tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

173

WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

307

WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

489

tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

492

WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

502

tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

505

WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

162

tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

165

WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

178

WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

330

tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

332

WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

345

tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

348

WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

376

orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

380

WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

187

data = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

190

WREG32(mmVCE_UENC_CLOCK_GATING, data);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

213

data = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

215

WREG32(mmVCE_UENC_CLOCK_GATING, data);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

559

WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

794

data = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

797

WREG32(mmVCE_UENC_CLOCK_GATING, data);

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

641

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), 0x1FF000, ~0xFF9FF000);