mt7601u_rr
val = mt7601u_rr(dev, MT_MAC_CSR0);
cur = mt7601u_rr(dev, offset) & mask;
cur = mt7601u_rr(dev, offset) & mask;
val = mt7601u_rr(dev, MT_TX_ALC_CFG_0);
val = ((mt7601u_rr(dev, MT_TX_PWR_CFG_1) & 0x0000ff00) >> 8);
val |= ((mt7601u_rr(dev, MT_TX_PWR_CFG_2) & 0x0000ff00) << 8);
val = ((mt7601u_rr(dev, MT_TX_PWR_CFG_4) & 0x0000ff00) >> 8);
mt7601u_rr(dev, MT_RX_STA_CNT0);
mt7601u_rr(dev, MT_RX_STA_CNT1);
mt7601u_rr(dev, MT_RX_STA_CNT2);
mt7601u_rr(dev, MT_TX_STA_CNT0);
mt7601u_rr(dev, MT_TX_STA_CNT1);
mt7601u_rr(dev, MT_TX_STA_CNT2);
val = mt7601u_rr(dev, MT_CMB_CTRL);
val = mt7601u_rr(dev, MT_WLAN_FUN_CTRL);
val = mt7601u_rr(dev, MT_TX_STAT_FIFO);
u32 val = mt7601u_rr(dev, MT_BEACON_TIME_CFG);
u32 val = mt7601u_rr(dev, 0x10f4);
u32 val = mt7601u_rr(dev, spans[i].addr_base + j * 4);
val = mt7601u_rr(dev, MT_WCID_ATTR(idx));
return mt7601u_rr(dev, MT_MCU_COM_REG0) == 1;
val = mt7601u_rr(dev, MT_TX_CPU_FROM_FCE_CPU_DESC_IDX);
u32 mt7601u_rr(struct mt7601u_dev *dev, u32 offset);
return mt7601u_rr(dev, offset);
mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL);
old = mt7601u_rr(dev, MT_MAC_SYS_CTRL);
dev->rf_pa_mode[0] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG0);
dev->rf_pa_mode[1] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG1);
val = mt7601u_rr(dev, MT_BBP_CSR_CFG);
rf_set = mt7601u_rr(dev, MT_RF_SETTING_0);
rf_bp = mt7601u_rr(dev, MT_RF_BYPASS_0);
mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL);
val = mt7601u_rr(dev, MT_RF_CSR_CFG);
val = mt7601u_rr(dev, MT_TX_ALC_CFG_1);
asic_rev = mt7601u_rr(dev, MT_ASIC_VERSION);
mac_rev = mt7601u_rr(dev, MT_MAC_CSR0);
if (!(mt7601u_rr(dev, MT_EFUSE_CTRL) & MT_EFUSE_CTRL_SEL))