mt312_readreg
ret = mt312_readreg(state, VIT_MODE, &vit_mode);
ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h);
ret = mt312_readreg(state, FEC_STATUS, &fec_status);
ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
ret = mt312_readreg(state, CONFIG, &config_val);
ret = mt312_readreg(state, GPP_CTRL, &val);
ret = mt312_readreg(state, CONFIG, &config);
if (mt312_readreg(state, ID, &state->id) < 0)