mt2712_writel
mt2712_writel(mt2712_rtc, MT2712_WRTGR, 1);
mt2712_writel(mt2712_rtc, MT2712_PROT, MT2712_PROT_UNLOCK1);
mt2712_writel(mt2712_rtc, MT2712_PROT, MT2712_PROT_UNLOCK2);
mt2712_writel(mt2712_rtc, MT2712_TC_SEC, tm->tm_sec & MT2712_SEC_MASK);
mt2712_writel(mt2712_rtc, MT2712_TC_MIN, tm->tm_min & MT2712_MIN_MASK);
mt2712_writel(mt2712_rtc, MT2712_TC_HOU, tm->tm_hour & MT2712_HOU_MASK);
mt2712_writel(mt2712_rtc, MT2712_TC_DOM, tm->tm_mday & MT2712_DOM_MASK);
mt2712_writel(mt2712_rtc, MT2712_TC_MTH,
mt2712_writel(mt2712_rtc, MT2712_TC_YEA,
mt2712_writel(mt2712_rtc, MT2712_IRQ_EN, irqen);
mt2712_writel(mt2712_rtc, MT2712_AL_SEC,
mt2712_writel(mt2712_rtc, MT2712_AL_MIN,
mt2712_writel(mt2712_rtc, MT2712_AL_HOU,
mt2712_writel(mt2712_rtc, MT2712_AL_DOM,
mt2712_writel(mt2712_rtc, MT2712_AL_MTH,
mt2712_writel(mt2712_rtc, MT2712_AL_YEA,
mt2712_writel(mt2712_rtc, MT2712_AL_MASK, MT2712_AL_MASK_DOW);
mt2712_writel(mt2712_rtc, MT2712_BBPU,
mt2712_writel(mt2712_rtc, MT2712_CII_EN, 0);
mt2712_writel(mt2712_rtc, MT2712_AL_MASK, 0);
mt2712_writel(mt2712_rtc, MT2712_CON0, 0x4848);
mt2712_writel(mt2712_rtc, MT2712_CON1, 0x0048);
mt2712_writel(mt2712_rtc, MT2712_POWERKEY1, MT2712_POWERKEY1_KEY);
mt2712_writel(mt2712_rtc, MT2712_POWERKEY2, MT2712_POWERKEY2_KEY);