drivers/gpu/drm/msm/msm_drv.h

46

struct msm_mdss;

drivers/gpu/drm/msm/msm_mdss.c

106

struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd);

drivers/gpu/drm/msm/msm_mdss.c

110

clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);

drivers/gpu/drm/msm/msm_mdss.c

117

struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd);

drivers/gpu/drm/msm/msm_mdss.c

121

set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);

drivers/gpu/drm/msm/msm_mdss.c

137

struct msm_mdss *msm_mdss = domain->host_data;

drivers/gpu/drm/msm/msm_mdss.c

142

return irq_set_chip_data(irq, msm_mdss);

drivers/gpu/drm/msm/msm_mdss.c

150

static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss)

drivers/gpu/drm/msm/msm_mdss.c

155

dev = msm_mdss->dev;

drivers/gpu/drm/msm/msm_mdss.c

157

domain = irq_domain_create_linear(dev_fwnode(dev), 32, &msm_mdss_irqdomain_ops, msm_mdss);

drivers/gpu/drm/msm/msm_mdss.c

163

msm_mdss->irq_controller.enabled_mask = 0;

drivers/gpu/drm/msm/msm_mdss.c

164

msm_mdss->irq_controller.domain = domain;

drivers/gpu/drm/msm/msm_mdss.c

169

static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss)

drivers/gpu/drm/msm/msm_mdss.c

171

const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;

drivers/gpu/drm/msm/msm_mdss.c

181

writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);

drivers/gpu/drm/msm/msm_mdss.c

184

static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss)

drivers/gpu/drm/msm/msm_mdss.c

186

const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;

drivers/gpu/drm/msm/msm_mdss.c

199

writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);

drivers/gpu/drm/msm/msm_mdss.c

202

static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss)

drivers/gpu/drm/msm/msm_mdss.c

204

const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;

drivers/gpu/drm/msm/msm_mdss.c

214

writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);

drivers/gpu/drm/msm/msm_mdss.c

217

writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);

drivers/gpu/drm/msm/msm_mdss.c

218

writel_relaxed(0, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);

drivers/gpu/drm/msm/msm_mdss.c

221

writel_relaxed(3, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);

drivers/gpu/drm/msm/msm_mdss.c

223

writel_relaxed(2, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);

drivers/gpu/drm/msm/msm_mdss.c

224

writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);

drivers/gpu/drm/msm/msm_mdss.c

228

static void msm_mdss_setup_ubwc_dec_50(struct msm_mdss *msm_mdss)

drivers/gpu/drm/msm/msm_mdss.c

230

const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;

drivers/gpu/drm/msm/msm_mdss.c

240

writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);

drivers/gpu/drm/msm/msm_mdss.c

243

writel_relaxed(5, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);

drivers/gpu/drm/msm/msm_mdss.c

245

writel_relaxed(4, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);

drivers/gpu/drm/msm/msm_mdss.c

247

writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);

drivers/gpu/drm/msm/msm_mdss.c

250

static int msm_mdss_enable(struct msm_mdss *msm_mdss)

drivers/gpu/drm/msm/msm_mdss.c

259

for (i = 0; i < msm_mdss->num_mdp_paths; i++)

drivers/gpu/drm/msm/msm_mdss.c

260

icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW));

drivers/gpu/drm/msm/msm_mdss.c

262

icc_set_bw(msm_mdss->reg_bus_path, 0,

drivers/gpu/drm/msm/msm_mdss.c

263

msm_mdss->reg_bus_bw);

drivers/gpu/drm/msm/msm_mdss.c

265

ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks);

drivers/gpu/drm/msm/msm_mdss.c

267

dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret);

drivers/gpu/drm/msm/msm_mdss.c

275

if (msm_mdss->is_mdp5 || !msm_mdss->mdss_data)

drivers/gpu/drm/msm/msm_mdss.c

285

switch (msm_mdss->mdss_data->ubwc_dec_version) {

drivers/gpu/drm/msm/msm_mdss.c

291

msm_mdss_setup_ubwc_dec_20(msm_mdss);

drivers/gpu/drm/msm/msm_mdss.c

294

msm_mdss_setup_ubwc_dec_30(msm_mdss);

drivers/gpu/drm/msm/msm_mdss.c

298

msm_mdss_setup_ubwc_dec_40(msm_mdss);

drivers/gpu/drm/msm/msm_mdss.c

301

msm_mdss_setup_ubwc_dec_50(msm_mdss);

drivers/gpu/drm/msm/msm_mdss.c

304

msm_mdss_setup_ubwc_dec_50(msm_mdss);

drivers/gpu/drm/msm/msm_mdss.c

307

dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n",

drivers/gpu/drm/msm/msm_mdss.c

308

msm_mdss->mdss_data->ubwc_dec_version);

drivers/gpu/drm/msm/msm_mdss.c

309

dev_err(msm_mdss->dev, "HW_REV: 0x%x\n",

drivers/gpu/drm/msm/msm_mdss.c

310

readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_VERSION));

drivers/gpu/drm/msm/msm_mdss.c

311

dev_err(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n",

drivers/gpu/drm/msm/msm_mdss.c

312

readl_relaxed(msm_mdss->mmio + REG_MDSS_UBWC_DEC_HW_VERSION));

drivers/gpu/drm/msm/msm_mdss.c

319

static int msm_mdss_disable(struct msm_mdss *msm_mdss)

drivers/gpu/drm/msm/msm_mdss.c

323

clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks);

drivers/gpu/drm/msm/msm_mdss.c

325

for (i = 0; i < msm_mdss->num_mdp_paths; i++)

drivers/gpu/drm/msm/msm_mdss.c

326

icc_set_bw(msm_mdss->mdp_path[i], 0, 0);

drivers/gpu/drm/msm/msm_mdss.c

328

if (msm_mdss->reg_bus_path)

drivers/gpu/drm/msm/msm_mdss.c

329

icc_set_bw(msm_mdss->reg_bus_path, 0, 0);

drivers/gpu/drm/msm/msm_mdss.c

334

static void msm_mdss_destroy(struct msm_mdss *msm_mdss)

drivers/gpu/drm/msm/msm_mdss.c

336

struct platform_device *pdev = to_platform_device(msm_mdss->dev);

drivers/gpu/drm/msm/msm_mdss.c

339

pm_runtime_suspend(msm_mdss->dev);

drivers/gpu/drm/msm/msm_mdss.c

340

pm_runtime_disable(msm_mdss->dev);

drivers/gpu/drm/msm/msm_mdss.c

341

irq_domain_remove(msm_mdss->irq_controller.domain);

drivers/gpu/drm/msm/msm_mdss.c

342

msm_mdss->irq_controller.domain = NULL;

drivers/gpu/drm/msm/msm_mdss.c

403

static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5)

drivers/gpu/drm/msm/msm_mdss.c

406

struct msm_mdss *msm_mdss;

drivers/gpu/drm/msm/msm_mdss.c

414

msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL);

drivers/gpu/drm/msm/msm_mdss.c

415

if (!msm_mdss)

drivers/gpu/drm/msm/msm_mdss.c

418

msm_mdss->mdss_data = qcom_ubwc_config_get_data();

drivers/gpu/drm/msm/msm_mdss.c

419

if (IS_ERR(msm_mdss->mdss_data))

drivers/gpu/drm/msm/msm_mdss.c

420

return ERR_CAST(msm_mdss->mdss_data);

drivers/gpu/drm/msm/msm_mdss.c

426

msm_mdss->reg_bus_bw = mdss_data->reg_bus_bw;

drivers/gpu/drm/msm/msm_mdss.c

428

msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss");

drivers/gpu/drm/msm/msm_mdss.c

429

if (IS_ERR(msm_mdss->mmio))

drivers/gpu/drm/msm/msm_mdss.c

430

return ERR_CAST(msm_mdss->mmio);

drivers/gpu/drm/msm/msm_mdss.c

432

dev_dbg(&pdev->dev, "mapped mdss address space @%p\n", msm_mdss->mmio);

drivers/gpu/drm/msm/msm_mdss.c

434

ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss);

drivers/gpu/drm/msm/msm_mdss.c

439

ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks);

drivers/gpu/drm/msm/msm_mdss.c

441

ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks);

drivers/gpu/drm/msm/msm_mdss.c

446

msm_mdss->num_clocks = ret;

drivers/gpu/drm/msm/msm_mdss.c

447

msm_mdss->is_mdp5 = is_mdp5;

drivers/gpu/drm/msm/msm_mdss.c

449

msm_mdss->dev = &pdev->dev;

drivers/gpu/drm/msm/msm_mdss.c

455

ret = _msm_mdss_irq_domain_add(msm_mdss);

drivers/gpu/drm/msm/msm_mdss.c

460

msm_mdss);

drivers/gpu/drm/msm/msm_mdss.c

464

return msm_mdss;

drivers/gpu/drm/msm/msm_mdss.c

469

struct msm_mdss *mdss = dev_get_drvdata(dev);

drivers/gpu/drm/msm/msm_mdss.c

478

struct msm_mdss *mdss = dev_get_drvdata(dev);

drivers/gpu/drm/msm/msm_mdss.c

50

struct msm_mdss *msm_mdss)

drivers/gpu/drm/msm/msm_mdss.c

509

struct msm_mdss *mdss;

drivers/gpu/drm/msm/msm_mdss.c

538

struct msm_mdss *mdss = platform_get_drvdata(pdev);

drivers/gpu/drm/msm/msm_mdss.c

60

msm_mdss->mdp_path[0] = path0;

drivers/gpu/drm/msm/msm_mdss.c

61

msm_mdss->num_mdp_paths = 1;

drivers/gpu/drm/msm/msm_mdss.c

65

msm_mdss->mdp_path[1] = path1;

drivers/gpu/drm/msm/msm_mdss.c

66

msm_mdss->num_mdp_paths++;

drivers/gpu/drm/msm/msm_mdss.c

71

msm_mdss->reg_bus_path = reg_bus_path;

drivers/gpu/drm/msm/msm_mdss.c

78

struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc);

drivers/gpu/drm/msm/msm_mdss.c

84

interrupts = readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_INTR_STATUS);

drivers/gpu/drm/msm/msm_mdss.c

90

rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain,

drivers/gpu/drm/msm/msm_mdss.c

93

dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n",