msm_dp_write_p0
msm_dp_write_p0(panel, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl);
msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period *
msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width *
msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0);
msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0);
msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl);
msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_HCTL, 0);
msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F0, display_v_start);
msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end);
msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F1, 0);
msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F1, 0);
msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F0, 0);
msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F0, 0);
msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F1, 0);
msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F1, 0);
msm_dp_write_p0(panel, MMSS_DP_INTF_POLARITY_CTL, 0);
msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL,
msm_dp_write_p0(panel, MMSS_DP_TPG_VIDEO_CONFIG,
msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE,
msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN,
msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, 0x0);
msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, 0x0);
msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, 0x0);
msm_dp_write_p0(panel, MMSS_DP_DSC_DTO, 0x0);
msm_dp_write_p0(panel, MMSS_DP_INTF_CONFIG, reg);