msm_dp_write_link
msm_dp_write_link(audio, MMSS_DP_AUDIO_COPYMANAGEMENT_0, header[0]);
msm_dp_write_link(audio, MMSS_DP_AUDIO_COPYMANAGEMENT_1, header[1]);
msm_dp_write_link(audio, MMSS_DP_AUDIO_ISRC_0, header[0]);
msm_dp_write_link(audio, MMSS_DP_AUDIO_ISRC_1, header[1]);
msm_dp_write_link(audio, MMSS_DP_SDP_CFG, sdp_cfg);
msm_dp_write_link(audio, MMSS_DP_SDP_CFG2, sdp_cfg2);
msm_dp_write_link(audio, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl);
msm_dp_write_link(audio, REG_DP_MAINLINK_LEVELS, mainlink_levels);
msm_dp_write_link(audio, MMSS_DP_AUDIO_CFG, audio_ctrl);
msm_dp_write_link(audio, MMSS_DP_AUDIO_STREAM_0, header[0]);
msm_dp_write_link(audio, MMSS_DP_AUDIO_STREAM_1, header[1]);
msm_dp_write_link(audio, MMSS_DP_AUDIO_TIMESTAMP_0, header[0]);
msm_dp_write_link(audio, MMSS_DP_AUDIO_TIMESTAMP_1, header[1]);
msm_dp_write_link(audio, MMSS_DP_AUDIO_INFOFRAME_0, header[0]);
msm_dp_write_link(audio, MMSS_DP_AUDIO_INFOFRAME_1, header[1]);
msm_dp_write_link(ctrl, REG_DP_VALID_BOUNDARY, valid_boundary);
msm_dp_write_link(ctrl, REG_DP_TU, msm_dp_tu);
msm_dp_write_link(ctrl, REG_DP_VALID_BOUNDARY_2, valid_boundary2);
msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, bit);
msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0);
msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0);
msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0);
msm_dp_write_link(ctrl, MMSS_DP_SDP_CFG3, UPDATE_SDP);
msm_dp_write_link(ctrl, MMSS_DP_SDP_CFG3, 0x0);
msm_dp_write_link(ctrl, REG_PSR_CMD, cmd);
msm_dp_write_link(ctrl, REG_PSR_CMD, cmd);
msm_dp_write_link(ctrl, REG_PSR_CONFIG, cfg);
msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0);
msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO);
msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0);
msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO);
msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0x0);
msm_dp_write_link(ctrl, REG_DP_STATE_CTRL,
msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET,
msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET,
msm_dp_write_link(ctrl, REG_DP_MAINLINK_LEVELS,
msm_dp_write_link(ctrl, REG_DP_STATE_CTRL,
msm_dp_write_link(ctrl, REG_DP_STATE_CTRL,
msm_dp_write_link(ctrl, REG_DP_STATE_CTRL,
msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0,
msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1,
msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2,
msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, value);
msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET,
msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET,
msm_dp_write_link(ctrl, REG_DP_MAINLINK_LEVELS,
msm_dp_write_link(ctrl, REG_DP_STATE_CTRL,
msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, value);
msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL,
msm_dp_write_link(ctrl, REG_DP_STATE_CTRL,
msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID, mvid);
msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid);
msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO);
msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, val);
msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, val);
msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_PUSH_IDLE);
msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config);
msm_dp_write_link(ctrl, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING,
msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val);
msm_dp_write_link(panel, MMSS_DP_GENERIC0_0, header[0]);
msm_dp_write_link(panel, MMSS_DP_GENERIC0_1, header[1]);
msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i, val);
msm_dp_write_link(panel, MMSS_DP_SDP_CFG3, UPDATE_SDP);
msm_dp_write_link(panel, MMSS_DP_SDP_CFG3, 0x0);
msm_dp_write_link(panel, MMSS_DP_SDP_CFG, cfg);
msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2);
msm_dp_write_link(panel, REG_DP_MISC1_MISC0, misc);
msm_dp_write_link(panel, MMSS_DP_SDP_CFG, cfg);
msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2);
msm_dp_write_link(panel, REG_DP_MISC1_MISC0, misc);
msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER, total);
msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC, sync_start);
msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blanking);
msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER, msm_dp_active);