drivers/gpu/drm/msm/dp/dp_ctrl.c

1915

msm_dp_write_ahb(ctrl, REG_DP_PHY_CTRL,

drivers/gpu/drm/msm/dp/dp_ctrl.c

1918

msm_dp_write_ahb(ctrl, REG_DP_PHY_CTRL, 0x0);

drivers/gpu/drm/msm/dp/dp_ctrl.c

214

msm_dp_write_ahb(ctrl, REG_DP_SW_RESET, sw_reset);

drivers/gpu/drm/msm/dp/dp_ctrl.c

218

msm_dp_write_ahb(ctrl, REG_DP_SW_RESET, sw_reset);

drivers/gpu/drm/msm/dp/dp_ctrl.c

234

msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS,

drivers/gpu/drm/msm/dp/dp_ctrl.c

249

msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2,

drivers/gpu/drm/msm/dp/dp_ctrl.c

260

msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS,

drivers/gpu/drm/msm/dp/dp_ctrl.c

262

msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2,

drivers/gpu/drm/msm/dp/dp_ctrl.c

271

msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS, 0x00);

drivers/gpu/drm/msm/dp/dp_ctrl.c

272

msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, 0x00);

drivers/gpu/drm/msm/dp/dp_ctrl.c

282

msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS4, intr_ack);

drivers/gpu/drm/msm/dp/dp_ctrl.c

289

msm_dp_write_ahb(ctrl, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4);