drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c

193

sizeof(struct msix_offset_rsp));

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

455

struct msix_offset_rsp *rsp_msix;

drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c

475

rsp_msix = (struct msix_offset_rsp *) msg;

drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c

108

rsp_msix = (struct msix_offset_rsp *) msg;

drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c

77

struct msix_offset_rsp *rsp_msix;

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

147

M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \

drivers/net/ethernet/marvell/octeontx2/af/rvu.c

1890

struct msix_offset_rsp *rsp)

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

1908

struct msix_offset_rsp *rsp)

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h

1083

struct msix_offset_rsp *rsp);

drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c

817

mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg);

drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c

67

mbox_handler_msix_offset(vf, (struct msix_offset_rsp *)msg);