CMD2
buf[5] = readl(mmio + CMD2);
writel(VAL2 | PROM, lp->mmio + CMD2);
writel(PROM, lp->mmio + CMD2);
writel(PROM, lp->mmio + CMD2);
readl(lp->mmio + CMD2);
writel(REX_UFLO, mmio + CMD2);
writel(VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2);
writel(VAL0 | APAD_XMT | REX_RTRY | REX_UFLO, mmio + CMD2);
writel(VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2);
writel(CMD2_CLEAR, mmio + CMD2);
readl(mmio + CMD2);
CMD2(0xd7, 0x08, 0x04), /* Blanking period control (2) */
CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */
CMD2(0xde, 0x05, 0x0a), /* OEV timing control */
CMD2(0xdf, 0x0a, 0x19), /* ASW timing control (1) */
CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */
CMD2(0xd2, 0x00, 0x1e), /* CKV 1,2 timing control */
CMD2(0xd3, 0x14, 0x28), /* OEV timing control */
CMD2(0xd4, 0x28, 0x64), /* ASW timing control (1) */
CMD2(0xb8, 0xff, 0xf9), /* Output control */
CMD2(0xc3, 0x20, 0x40), /* Sleep out FR count (D) */
CMD2(0xc4, 0x60, 0xc0), /* Sleep out FR count (E) */
CMD2(0xc5, 0x10, 0x20), /* Sleep out FR count (F) */
CMD2(0xc7, 0x33, 0x43), /* Gamma 1 fine tuning (1) */
CMD2(0xec, 0x01, 0xf0), /* Horizontal clock cycles */
CMD2(0xB8, 0xFF, 0xF9), /* Output Control */
CMD2(0xB8, 0x80, 0x02), /* Output Control */
CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */
CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */