mr32
tmp = mr32(MVS_INT_STAT_SRS_0);
tmp = mr32(MVS_INT_STAT_SRS_0);
tmp = mr32(MVS_GBL_CTL);
tmp = mr32(MVS_GBL_CTL);
if (!(mr32(MVS_GBL_CTL) & HBA_RST))
if (mr32(MVS_GBL_CTL) & HBA_RST) {
reg = mr32(MVS_GBL_PORT_TYPE);
tmp = mr32(MVS_PHY_CTL);
tmp = mr32(MVS_PHY_CTL);
tmp = mr32(MVS_PHY_CTL);
cctl = mr32(MVS_CTL) & 0xFFFF;
tmp = mr32(MVS_PHY_CTL);
tmp = mr32(MVS_PCS);
cctl = mr32(MVS_CTL);
tmp = mr32(MVS_PCS);
tmp = mr32(MVS_GBL_CTL);
tmp = mr32(MVS_GBL_CTL);
stat = mr32(MVS_GBL_INT_STAT);
tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs);
tmp = mr32(MVS_PCS) | 0xFF00;
tmp = mr32(MVS_PCS);
tmp = mr32(MVS_CTL);
tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << *tfs);
tmp = mr32(MVS_PCS);
tmp = mr32(MVS_CTL);
tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << i);
tmp = mr32(MVS_PCS);
tmp = mr32(MVS_CTL);
reg = mr32(MVS_PHY_CTL);
tmp = mr32(MVS_PCS);
tmp = mr32(MVS_HST_CHIP_CONFIG);
tmp = mr32(MVS_PHY_CTL);
cctl = mr32(MVS_CTL) & 0xFFFF;
tmp = mr32(MVS_PHY_CTL);
tmp = mr32(MVS_PA_VSR_PORT);
cctl = mr32(MVS_CTL);
tmp = mr32(MVS_PCS);
tmp = mr32(MVS_GBL_CTL);
tmp = mr32(MVS_GBL_CTL);
stat = mr32(MVS_GBL_INT_STAT);
tmp = mr32(MVS_INT_STAT_SRS_0);
tmp = mr32(MVS_INT_STAT_SRS_1);
tmp = mr32(MVS_INT_STAT_SRS_1);
tmp = mr32(MVS_INT_STAT_SRS_0);
tmp = mr32(MVS_INT_STAT);
tmp = mr32(MVS_PCS) | 0xFF00;
err_0 = mr32(MVS_NON_NCQ_ERR_0);
err_1 = mr32(MVS_NON_NCQ_ERR_1);
tmp = mr32(MVS_STP_REG_SET_0);
tmp = mr32(MVS_STP_REG_SET_1);
return mr32(SPI_RD_DATA_REG_94XX);
dwTmp = mr32(SPI_CTRL_REG_94XX);
(((i) > 31) ? mr32(MVS_STP_REG_SET_1) : \
mr32(MVS_STP_REG_SET_0))
tmp = mr32(MVS_INT_STAT_SRS_0);
mr32(reg); \
stat = mr32(MVS_INT_STAT);
return mr32(MVS_RX_CONS_IDX);
return mr32(MVS_CMD_DATA);
return (port < 4) ? mr32(MVS_P0_SER_CTLSTAT + port * 4) :
mr32(MVS_P4_SER_CTLSTAT + (port - 4) * 4);