drivers/gpu/drm/amd/amdgpu/cik_sdma.c

180

return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

194

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

463

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

479

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

204

u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

220

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

438

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

454

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

368

wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

395

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

715

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1103

WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

682

wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

725

WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

92

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

356

wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

398

ring->me, mmSDMA0_GFX_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

718

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

723

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

760

WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

79

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

196

wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

234

WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

247

WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

567

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

572

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

608

WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

80

SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),