drivers/clk/imx/clk-imx25.c

82

clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL));

drivers/clk/imx/clk-imx31.c

58

clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL);

drivers/clk/imx/clk-imx35.c

108

clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL);

drivers/clk/imx/clk-imx35.c

111

clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4);

drivers/clk/meson/clk-mpll.c

113

struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);

drivers/clk/meson/clk-mpll.c

116

params_from_rate(rate, parent_rate, &sdm, &n2, mpll->flags);

drivers/clk/meson/clk-mpll.c

119

meson_parm_write(clk->map, &mpll->sdm, sdm);

drivers/clk/meson/clk-mpll.c

122

meson_parm_write(clk->map, &mpll->n2, n2);

drivers/clk/meson/clk-mpll.c

130

struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);

drivers/clk/meson/clk-mpll.c

137

if (mpll->init_count)

drivers/clk/meson/clk-mpll.c

138

regmap_multi_reg_write(clk->map, mpll->init_regs,

drivers/clk/meson/clk-mpll.c

139

mpll->init_count);

drivers/clk/meson/clk-mpll.c

142

meson_parm_write(clk->map, &mpll->sdm_en, 1);

drivers/clk/meson/clk-mpll.c

145

if (MESON_PARM_APPLICABLE(&mpll->ssen)) {

drivers/clk/meson/clk-mpll.c

147

mpll->flags & CLK_MESON_MPLL_SPREAD_SPECTRUM ? 1 : 0;

drivers/clk/meson/clk-mpll.c

148

meson_parm_write(clk->map, &mpll->ssen, ss);

drivers/clk/meson/clk-mpll.c

152

if (MESON_PARM_APPLICABLE(&mpll->misc))

drivers/clk/meson/clk-mpll.c

153

meson_parm_write(clk->map, &mpll->misc, 1);

drivers/clk/meson/clk-mpll.c

79

struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);

drivers/clk/meson/clk-mpll.c

83

sdm = meson_parm_read(clk->map, &mpll->sdm);

drivers/clk/meson/clk-mpll.c

84

n2 = meson_parm_read(clk->map, &mpll->n2);

drivers/clk/meson/clk-mpll.c

93

struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);

drivers/clk/meson/clk-mpll.c

98

mpll->flags);

drivers/clk/mstar/clk-msc313-mpll.c

100

mpll->loop_div_first = devm_regmap_field_alloc(dev, regmap, config1_loop_div_first);

drivers/clk/mstar/clk-msc313-mpll.c

101

if (IS_ERR(mpll->loop_div_first))

drivers/clk/mstar/clk-msc313-mpll.c

102

return PTR_ERR(mpll->loop_div_first);

drivers/clk/mstar/clk-msc313-mpll.c

103

mpll->loop_div_second = devm_regmap_field_alloc(dev, regmap, config2_loop_div_second);

drivers/clk/mstar/clk-msc313-mpll.c

104

if (IS_ERR(mpll->loop_div_second))

drivers/clk/mstar/clk-msc313-mpll.c

105

return PTR_ERR(mpll->loop_div_second);

drivers/clk/mstar/clk-msc313-mpll.c

107

mpll->clk_data = devm_kzalloc(dev, struct_size(mpll->clk_data, hws,

drivers/clk/mstar/clk-msc313-mpll.c

109

if (!mpll->clk_data)

drivers/clk/mstar/clk-msc313-mpll.c

116

mpll->clk_hw.init = &clk_init;

drivers/clk/mstar/clk-msc313-mpll.c

118

ret = devm_clk_hw_register(dev, &mpll->clk_hw);

drivers/clk/mstar/clk-msc313-mpll.c

122

mpll->clk_data->num = NUMOUTPUTS;

drivers/clk/mstar/clk-msc313-mpll.c

123

mpll->clk_data->hws[0] = &mpll->clk_hw;

drivers/clk/mstar/clk-msc313-mpll.c

134

mpll->clk_data->hws[i + 1] = divhw;

drivers/clk/mstar/clk-msc313-mpll.c

137

platform_set_drvdata(pdev, mpll);

drivers/clk/mstar/clk-msc313-mpll.c

140

mpll->clk_data);

drivers/clk/mstar/clk-msc313-mpll.c

47

struct msc313_mpll *mpll = to_mpll(hw);

drivers/clk/mstar/clk-msc313-mpll.c

51

regmap_field_read(mpll->input_div, &input_div);

drivers/clk/mstar/clk-msc313-mpll.c

52

regmap_field_read(mpll->output_div, &output_div);

drivers/clk/mstar/clk-msc313-mpll.c

53

regmap_field_read(mpll->loop_div_first, &loop_first);

drivers/clk/mstar/clk-msc313-mpll.c

54

regmap_field_read(mpll->loop_div_second, &loop_second);

drivers/clk/mstar/clk-msc313-mpll.c

74

struct msc313_mpll *mpll;

drivers/clk/mstar/clk-msc313-mpll.c

82

mpll = devm_kzalloc(dev, sizeof(*mpll), GFP_KERNEL);

drivers/clk/mstar/clk-msc313-mpll.c

83

if (!mpll)

drivers/clk/mstar/clk-msc313-mpll.c

94

mpll->input_div = devm_regmap_field_alloc(dev, regmap, config1_input_div_first);

drivers/clk/mstar/clk-msc313-mpll.c

95

if (IS_ERR(mpll->input_div))

drivers/clk/mstar/clk-msc313-mpll.c

96

return PTR_ERR(mpll->input_div);

drivers/clk/mstar/clk-msc313-mpll.c

97

mpll->output_div = devm_regmap_field_alloc(dev, regmap, config2_output_div_first);

drivers/clk/mstar/clk-msc313-mpll.c

98

if (IS_ERR(mpll->output_div))

drivers/clk/mstar/clk-msc313-mpll.c

99

return PTR_ERR(mpll->output_div);

drivers/clk/samsung/clk-exynos4.c

1154

[mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",

drivers/clk/samsung/clk-exynos4.c

1165

[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",

drivers/clk/samsung/clk-exynos5250.c

739

[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,

drivers/clk/samsung/clk-exynos5410.c

247

[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,

drivers/clk/samsung/clk-exynos5420.c

1482

[mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,

drivers/clk/samsung/clk-s5pv210.c

717

[mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",

drivers/clk/samsung/clk-s5pv210.c

729

[mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",

drivers/gpu/drm/amd/amdgpu/amdgpu.h

379

struct amdgpu_pll mpll;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

591

struct amdgpu_pll *mpll = &adev->clock.mpll;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

663

mpll->reference_freq =

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

665

mpll->reference_div = 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

667

mpll->pll_out_min =

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

669

mpll->pll_out_max =

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

673

if (mpll->pll_out_min == 0)

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

674

mpll->pll_out_min = 64800;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

676

mpll->pll_in_min =

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

678

mpll->pll_in_max =

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

686

mpll->min_post_div = 1;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

687

mpll->max_post_div = 1;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

688

mpll->min_ref_div = 2;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

689

mpll->max_ref_div = 0xff;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

690

mpll->min_feedback_div = 4;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

691

mpll->max_feedback_div = 0xff;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

692

mpll->best_vco = 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

798

struct amdgpu_pll *mpll = &adev->clock.mpll;

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

857

mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

859

mpll->reference_div = 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

860

mpll->min_post_div = 1;

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

861

mpll->max_post_div = 1;

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

862

mpll->min_ref_div = 2;

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

863

mpll->max_ref_div = 0xff;

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

864

mpll->min_feedback_div = 4;

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

865

mpll->max_feedback_div = 0xff;

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

866

mpll->best_vco = 0;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

5457

u32 reference_clock = adev->clock.mpll.reference_freq;

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c

288

bool mpll = Preg == 0x4020;

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c

291

uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) |

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c

306

if (mpll) {

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c

322

Pval |= mpll ? 1 << 12 : 1 << 8;

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c

326

if (mpll) {

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c

340

if (mpll) {

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c

349

if (mpll) {

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

225

struct nvbios_pll mpll;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

327

ret = nvbios_pll_parse(bios, 0x004008, &mpll);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

328

mpll.vco2.max_freq = 0;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

330

ret = nv04_pll_calc(subdev, &mpll, freq,

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

348

r004008 |= (mpll.bias_p << 19) | (P << 22) | (P << 16);

drivers/gpu/drm/radeon/ci_dpm.c

2787

u32 reference_clock = rdev->clock.mpll.reference_freq;

drivers/gpu/drm/radeon/cypress_dpm.c

442

u32 ref_clk = rdev->clock.mpll.reference_freq;

drivers/gpu/drm/radeon/cypress_dpm.c

558

u32 reference_clock = rdev->clock.mpll.reference_freq;

drivers/gpu/drm/radeon/ni_dpm.c

2242

u32 reference_clock = rdev->clock.mpll.reference_freq;

drivers/gpu/drm/radeon/radeon.h

272

struct radeon_pll mpll;

drivers/gpu/drm/radeon/radeon_atombios.c

1136

struct radeon_pll *mpll = &rdev->clock.mpll;

drivers/gpu/drm/radeon/radeon_atombios.c

1215

mpll->reference_freq =

drivers/gpu/drm/radeon/radeon_atombios.c

1218

mpll->reference_freq =

drivers/gpu/drm/radeon/radeon_atombios.c

1220

mpll->reference_div = 0;

drivers/gpu/drm/radeon/radeon_atombios.c

1222

mpll->pll_out_min =

drivers/gpu/drm/radeon/radeon_atombios.c

1224

mpll->pll_out_max =

drivers/gpu/drm/radeon/radeon_atombios.c

1228

if (mpll->pll_out_min == 0) {

drivers/gpu/drm/radeon/radeon_atombios.c

1230

mpll->pll_out_min = 64800;

drivers/gpu/drm/radeon/radeon_atombios.c

1232

mpll->pll_out_min = 20000;

drivers/gpu/drm/radeon/radeon_atombios.c

1235

mpll->pll_in_min =

drivers/gpu/drm/radeon/radeon_atombios.c

1237

mpll->pll_in_max =

drivers/gpu/drm/radeon/radeon_clocks.c

112

struct radeon_pll *mpll = &rdev->clock.mpll;

drivers/gpu/drm/radeon/radeon_clocks.c

150

spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;

drivers/gpu/drm/radeon/radeon_clocks.c

151

spll->reference_div = mpll->reference_div =

drivers/gpu/drm/radeon/radeon_clocks.c

187

struct radeon_pll *mpll = &rdev->clock.mpll;

drivers/gpu/drm/radeon/radeon_clocks.c

219

if (mpll->reference_div < 2)

drivers/gpu/drm/radeon/radeon_clocks.c

220

mpll->reference_div = spll->reference_div;

drivers/gpu/drm/radeon/radeon_clocks.c

234

mpll->reference_freq = 1432;

drivers/gpu/drm/radeon/radeon_clocks.c

239

mpll->reference_freq = 2700;

drivers/gpu/drm/radeon/radeon_clocks.c

270

mpll->reference_div = spll->reference_div;

drivers/gpu/drm/radeon/radeon_clocks.c

332

mpll->min_post_div = 1;

drivers/gpu/drm/radeon/radeon_clocks.c

333

mpll->max_post_div = 1;

drivers/gpu/drm/radeon/radeon_clocks.c

334

mpll->min_ref_div = 2;

drivers/gpu/drm/radeon/radeon_clocks.c

335

mpll->max_ref_div = 0xff;

drivers/gpu/drm/radeon/radeon_clocks.c

336

mpll->min_feedback_div = 4;

drivers/gpu/drm/radeon/radeon_clocks.c

337

mpll->max_feedback_div = 0xff;

drivers/gpu/drm/radeon/radeon_clocks.c

338

mpll->best_vco = 0;

drivers/gpu/drm/radeon/radeon_clocks.c

72

struct radeon_pll *mpll = &rdev->clock.mpll;

drivers/gpu/drm/radeon/radeon_clocks.c

78

fb_div *= mpll->reference_freq;

drivers/gpu/drm/radeon/radeon_combios.c

721

struct radeon_pll *mpll = &rdev->clock.mpll;

drivers/gpu/drm/radeon/radeon_combios.c

762

mpll->reference_freq = RBIOS16(pll_info + 0x26);

drivers/gpu/drm/radeon/radeon_combios.c

763

mpll->reference_div = RBIOS16(pll_info + 0x28);

drivers/gpu/drm/radeon/radeon_combios.c

764

mpll->pll_out_min = RBIOS32(pll_info + 0x2a);

drivers/gpu/drm/radeon/radeon_combios.c

765

mpll->pll_out_max = RBIOS32(pll_info + 0x2e);

drivers/gpu/drm/radeon/radeon_combios.c

768

mpll->pll_in_min = RBIOS32(pll_info + 0x5a);

drivers/gpu/drm/radeon/radeon_combios.c

769

mpll->pll_in_max = RBIOS32(pll_info + 0x5e);

drivers/gpu/drm/radeon/radeon_combios.c

772

mpll->pll_in_min = 40;

drivers/gpu/drm/radeon/radeon_combios.c

773

mpll->pll_in_max = 500;

drivers/gpu/drm/radeon/rv6xx_dpm.c

655

u32 ref_clk = rdev->clock.mpll.reference_freq;

drivers/gpu/drm/radeon/rv730_dpm.c

169

u32 reference_clock = rdev->clock.mpll.reference_freq;

drivers/gpu/drm/radeon/rv740_dpm.c

250

u32 reference_clock = rdev->clock.mpll.reference_freq;

drivers/gpu/drm/radeon/rv770_dpm.c

405

u32 reference_clock = rdev->clock.mpll.reference_freq;

drivers/gpu/drm/radeon/si_dpm.c

4862

u32 reference_clock = rdev->clock.mpll.reference_freq;

drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c

125

u32 mpll;

drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c

406

data |= SSPHY_MPLL(phy_dwc3->mpll);

drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c

532

if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll))

drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c

533

phy_dwc3->mpll = SSPHY_MPLL_VALUE;