Symbol: CM
arch/x86/mm/pat/memtype.c
190
case X86_MEMTYPE_UC: cache = CM(UC); cache_mode = "UC "; break;
arch/x86/mm/pat/memtype.c
191
case X86_MEMTYPE_WC: cache = CM(WC); cache_mode = "WC "; break;
arch/x86/mm/pat/memtype.c
192
case X86_MEMTYPE_WT: cache = CM(WT); cache_mode = "WT "; break;
arch/x86/mm/pat/memtype.c
193
case X86_MEMTYPE_WP: cache = CM(WP); cache_mode = "WP "; break;
arch/x86/mm/pat/memtype.c
194
case X86_MEMTYPE_WB: cache = CM(WB); cache_mode = "WB "; break;
arch/x86/mm/pat/memtype.c
195
case X86_MEMTYPE_UC_MINUS: cache = CM(UC_MINUS); cache_mode = "UC- "; break;
arch/x86/mm/pat/memtype.c
196
default: cache = CM(WB); cache_mode = "WB "; break;
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
100
SRI(CM_DGAM_RAMA_START_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
101
SRI(CM_DGAM_RAMA_SLOPE_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
102
SRI(CM_DGAM_RAMA_SLOPE_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
103
SRI(CM_DGAM_RAMA_SLOPE_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
104
SRI(CM_DGAM_RAMA_END_CNTL1_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
105
SRI(CM_DGAM_RAMA_END_CNTL2_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
106
SRI(CM_DGAM_RAMA_END_CNTL1_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
107
SRI(CM_DGAM_RAMA_END_CNTL2_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
108
SRI(CM_DGAM_RAMA_END_CNTL1_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
109
SRI(CM_DGAM_RAMA_END_CNTL2_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
110
SRI(CM_DGAM_RAMA_REGION_0_1, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
111
SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
112
SRI(CM_MEM_PWR_CTRL, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
113
SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
114
SRI(CM_DGAM_LUT_INDEX, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
115
SRI(CM_DGAM_LUT_DATA, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
116
SRI(CM_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
117
SRI(CM_DGAM_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
118
SRI(CM_TEST_DEBUG_INDEX, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
119
SRI(CM_TEST_DEBUG_DATA, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
127
SRI(CM_HDR_MULT_COEF, CM, id)
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
133
SRI(CM_COMA_C11_C12, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
134
SRI(CM_COMA_C33_C34, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
135
SRI(CM_COMB_C11_C12, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
136
SRI(CM_COMB_C33_C34, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
137
SRI(CM_OCSC_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
138
SRI(CM_OCSC_C11_C12, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
139
SRI(CM_OCSC_C33_C34, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
140
SRI(CM_BNS_VALUES_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
141
SRI(CM_BNS_VALUES_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
142
SRI(CM_BNS_VALUES_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
143
SRI(CM_MEM_PWR_CTRL, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
144
SRI(CM_RGAM_LUT_DATA, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
145
SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
146
SRI(CM_RGAM_LUT_INDEX, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
147
SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
148
SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
149
SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
150
SRI(CM_RGAM_RAMB_SLOPE_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
151
SRI(CM_RGAM_RAMB_SLOPE_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
152
SRI(CM_RGAM_RAMB_SLOPE_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
153
SRI(CM_RGAM_RAMB_END_CNTL1_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
154
SRI(CM_RGAM_RAMB_END_CNTL2_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
155
SRI(CM_RGAM_RAMB_END_CNTL1_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
156
SRI(CM_RGAM_RAMB_END_CNTL2_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
157
SRI(CM_RGAM_RAMB_END_CNTL1_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
158
SRI(CM_RGAM_RAMB_END_CNTL2_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
159
SRI(CM_RGAM_RAMB_REGION_0_1, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
160
SRI(CM_RGAM_RAMB_REGION_32_33, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
161
SRI(CM_RGAM_RAMA_START_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
162
SRI(CM_RGAM_RAMA_START_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
163
SRI(CM_RGAM_RAMA_START_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
164
SRI(CM_RGAM_RAMA_SLOPE_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
165
SRI(CM_RGAM_RAMA_SLOPE_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
166
SRI(CM_RGAM_RAMA_SLOPE_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
167
SRI(CM_RGAM_RAMA_END_CNTL1_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
168
SRI(CM_RGAM_RAMA_END_CNTL2_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
169
SRI(CM_RGAM_RAMA_END_CNTL1_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
170
SRI(CM_RGAM_RAMA_END_CNTL2_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
171
SRI(CM_RGAM_RAMA_END_CNTL1_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
172
SRI(CM_RGAM_RAMA_END_CNTL2_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
173
SRI(CM_RGAM_RAMA_REGION_0_1, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
174
SRI(CM_RGAM_RAMA_REGION_32_33, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
175
SRI(CM_RGAM_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
176
SRI(CM_IGAM_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
177
SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
178
SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
179
SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
181
SRI(CM_CMOUT_CONTROL, CM, id)
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
45
SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
46
SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
47
SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
48
SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
49
SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
50
SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
51
SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
81
SRI(CM_ICSC_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
82
SRI(CM_ICSC_C11_C12, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
83
SRI(CM_ICSC_C33_C34, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
84
SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
85
SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
86
SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
87
SRI(CM_DGAM_RAMB_SLOPE_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
88
SRI(CM_DGAM_RAMB_SLOPE_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
89
SRI(CM_DGAM_RAMB_SLOPE_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
90
SRI(CM_DGAM_RAMB_END_CNTL1_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
91
SRI(CM_DGAM_RAMB_END_CNTL2_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
92
SRI(CM_DGAM_RAMB_END_CNTL1_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
93
SRI(CM_DGAM_RAMB_END_CNTL2_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
94
SRI(CM_DGAM_RAMB_END_CNTL1_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
95
SRI(CM_DGAM_RAMB_END_CNTL2_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
96
SRI(CM_DGAM_RAMB_REGION_0_1, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
97
SRI(CM_DGAM_RAMB_REGION_14_15, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
98
SRI(CM_DGAM_RAMA_START_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
99
SRI(CM_DGAM_RAMA_START_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
100
SRI(CM_3DLUT_DATA_30BIT, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
101
SRI(CM_3DLUT_READ_WRITE_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
102
SRI(CM_SHAPER_LUT_WRITE_EN_MASK, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
103
SRI(CM_SHAPER_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
104
SRI(CM_SHAPER_RAMB_START_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
105
SRI(CM_SHAPER_RAMB_START_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
106
SRI(CM_SHAPER_RAMB_START_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
107
SRI(CM_SHAPER_RAMB_END_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
108
SRI(CM_SHAPER_RAMB_END_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
109
SRI(CM_SHAPER_RAMB_END_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
110
SRI(CM_SHAPER_RAMB_REGION_0_1, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
111
SRI(CM_SHAPER_RAMB_REGION_2_3, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
112
SRI(CM_SHAPER_RAMB_REGION_4_5, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
113
SRI(CM_SHAPER_RAMB_REGION_6_7, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
114
SRI(CM_SHAPER_RAMB_REGION_8_9, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
115
SRI(CM_SHAPER_RAMB_REGION_10_11, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
116
SRI(CM_SHAPER_RAMB_REGION_12_13, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
117
SRI(CM_SHAPER_RAMB_REGION_14_15, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
118
SRI(CM_SHAPER_RAMB_REGION_16_17, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
119
SRI(CM_SHAPER_RAMB_REGION_18_19, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
120
SRI(CM_SHAPER_RAMB_REGION_20_21, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
121
SRI(CM_SHAPER_RAMB_REGION_22_23, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
122
SRI(CM_SHAPER_RAMB_REGION_24_25, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
123
SRI(CM_SHAPER_RAMB_REGION_26_27, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
124
SRI(CM_SHAPER_RAMB_REGION_28_29, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
125
SRI(CM_SHAPER_RAMB_REGION_30_31, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
126
SRI(CM_SHAPER_RAMB_REGION_32_33, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
127
SRI(CM_SHAPER_RAMA_START_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
128
SRI(CM_SHAPER_RAMA_START_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
129
SRI(CM_SHAPER_RAMA_START_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
130
SRI(CM_SHAPER_RAMA_END_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
131
SRI(CM_SHAPER_RAMA_END_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
132
SRI(CM_SHAPER_RAMA_END_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
133
SRI(CM_SHAPER_RAMA_REGION_0_1, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
134
SRI(CM_SHAPER_RAMA_REGION_2_3, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
135
SRI(CM_SHAPER_RAMA_REGION_4_5, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
136
SRI(CM_SHAPER_RAMA_REGION_6_7, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
137
SRI(CM_SHAPER_RAMA_REGION_8_9, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
138
SRI(CM_SHAPER_RAMA_REGION_10_11, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
139
SRI(CM_SHAPER_RAMA_REGION_12_13, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
140
SRI(CM_SHAPER_RAMA_REGION_14_15, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
141
SRI(CM_SHAPER_RAMA_REGION_16_17, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
142
SRI(CM_SHAPER_RAMA_REGION_18_19, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
143
SRI(CM_SHAPER_RAMA_REGION_20_21, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
144
SRI(CM_SHAPER_RAMA_REGION_22_23, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
145
SRI(CM_SHAPER_RAMA_REGION_24_25, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
146
SRI(CM_SHAPER_RAMA_REGION_26_27, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
147
SRI(CM_SHAPER_RAMA_REGION_28_29, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
148
SRI(CM_SHAPER_RAMA_REGION_30_31, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
149
SRI(CM_SHAPER_RAMA_REGION_32_33, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
150
SRI(CM_SHAPER_LUT_INDEX, CM, id)
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
153
SRI(CM_GAMUT_REMAP_B_C11_C12, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
154
SRI(CM_GAMUT_REMAP_B_C13_C14, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
155
SRI(CM_GAMUT_REMAP_B_C21_C22, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
156
SRI(CM_GAMUT_REMAP_B_C23_C24, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
157
SRI(CM_GAMUT_REMAP_B_C31_C32, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
158
SRI(CM_GAMUT_REMAP_B_C33_C34, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
159
SRI(CM_ICSC_B_C11_C12, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
160
SRI(CM_ICSC_B_C33_C34, CM, id)
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
179
SRI(CM_SHAPER_LUT_DATA, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
33
SRI(CM_BLNDGAM_LUT_WRITE_EN_MASK, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
34
SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
35
SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
36
SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
37
SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
38
SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
39
SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM, id)
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
42
SRI(CM_BLNDGAM_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
43
SRI(CM_BLNDGAM_RAMB_START_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
44
SRI(CM_BLNDGAM_RAMB_START_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
45
SRI(CM_BLNDGAM_RAMB_START_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
46
SRI(CM_BLNDGAM_RAMB_END_CNTL1_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
47
SRI(CM_BLNDGAM_RAMB_END_CNTL2_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
48
SRI(CM_BLNDGAM_RAMB_END_CNTL1_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
49
SRI(CM_BLNDGAM_RAMB_END_CNTL2_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
50
SRI(CM_BLNDGAM_RAMB_END_CNTL1_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
51
SRI(CM_BLNDGAM_RAMB_END_CNTL2_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
52
SRI(CM_BLNDGAM_RAMB_REGION_0_1, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
53
SRI(CM_BLNDGAM_RAMB_REGION_2_3, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
54
SRI(CM_BLNDGAM_RAMB_REGION_4_5, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
55
SRI(CM_BLNDGAM_RAMB_REGION_6_7, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
56
SRI(CM_BLNDGAM_RAMB_REGION_8_9, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
57
SRI(CM_BLNDGAM_RAMB_REGION_10_11, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
58
SRI(CM_BLNDGAM_RAMB_REGION_12_13, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
59
SRI(CM_BLNDGAM_RAMB_REGION_14_15, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
60
SRI(CM_BLNDGAM_RAMB_REGION_16_17, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
61
SRI(CM_BLNDGAM_RAMB_REGION_18_19, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
62
SRI(CM_BLNDGAM_RAMB_REGION_20_21, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
63
SRI(CM_BLNDGAM_RAMB_REGION_22_23, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
64
SRI(CM_BLNDGAM_RAMB_REGION_24_25, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
65
SRI(CM_BLNDGAM_RAMB_REGION_26_27, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
66
SRI(CM_BLNDGAM_RAMB_REGION_28_29, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
67
SRI(CM_BLNDGAM_RAMB_REGION_30_31, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
68
SRI(CM_BLNDGAM_RAMB_REGION_32_33, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
69
SRI(CM_BLNDGAM_RAMA_START_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
70
SRI(CM_BLNDGAM_RAMA_START_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
71
SRI(CM_BLNDGAM_RAMA_START_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
72
SRI(CM_BLNDGAM_RAMA_END_CNTL1_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
73
SRI(CM_BLNDGAM_RAMA_END_CNTL2_B, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
74
SRI(CM_BLNDGAM_RAMA_END_CNTL1_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
75
SRI(CM_BLNDGAM_RAMA_END_CNTL2_G, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
76
SRI(CM_BLNDGAM_RAMA_END_CNTL1_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
77
SRI(CM_BLNDGAM_RAMA_END_CNTL2_R, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
78
SRI(CM_BLNDGAM_RAMA_REGION_0_1, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
79
SRI(CM_BLNDGAM_RAMA_REGION_2_3, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
80
SRI(CM_BLNDGAM_RAMA_REGION_4_5, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
81
SRI(CM_BLNDGAM_RAMA_REGION_6_7, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
82
SRI(CM_BLNDGAM_RAMA_REGION_8_9, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
83
SRI(CM_BLNDGAM_RAMA_REGION_10_11, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
84
SRI(CM_BLNDGAM_RAMA_REGION_12_13, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
85
SRI(CM_BLNDGAM_RAMA_REGION_14_15, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
86
SRI(CM_BLNDGAM_RAMA_REGION_16_17, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
87
SRI(CM_BLNDGAM_RAMA_REGION_18_19, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
88
SRI(CM_BLNDGAM_RAMA_REGION_20_21, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
89
SRI(CM_BLNDGAM_RAMA_REGION_22_23, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
90
SRI(CM_BLNDGAM_RAMA_REGION_24_25, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
91
SRI(CM_BLNDGAM_RAMA_REGION_26_27, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
92
SRI(CM_BLNDGAM_RAMA_REGION_28_29, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
93
SRI(CM_BLNDGAM_RAMA_REGION_30_31, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
94
SRI(CM_BLNDGAM_RAMA_REGION_32_33, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
95
SRI(CM_BLNDGAM_LUT_INDEX, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
96
SRI(CM_BLNDGAM_LUT_DATA, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
97
SRI(CM_3DLUT_MODE, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
98
SRI(CM_3DLUT_INDEX, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
99
SRI(CM_3DLUT_DATA, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
128
SRI(CM_POST_CSC_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
129
SRI(CM_POST_CSC_C11_C12, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
130
SRI(CM_POST_CSC_C33_C34, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
131
SRI(CM_POST_CSC_B_C11_C12, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
132
SRI(CM_POST_CSC_B_C33_C34, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
133
SRI(CM_MEM_PWR_CTRL, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
134
SRI(CM_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
135
SRI(CM_TEST_DEBUG_INDEX, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
136
SRI(CM_TEST_DEBUG_DATA, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
144
SRI(CM_HDR_MULT_COEF, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
166
SRI(CM_BLNDGAM_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
167
SRI(CM_SHAPER_LUT_DATA, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
168
SRI(CM_MEM_PWR_CTRL2, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
169
SRI(CM_MEM_PWR_STATUS2, CM, id), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
170
SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
171
SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
172
SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
173
SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
174
SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
175
SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
176
SRI(CM_BLNDGAM_LUT_CONTROL, CM, id)
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
34
SRI(CM_DEALPHA, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
35
SRI(CM_MEM_PWR_STATUS, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
36
SRI(CM_BIAS_CR_R, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
37
SRI(CM_BIAS_Y_G_CB_B, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
39
SRI(CM_GAMCOR_CONTROL, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
40
SRI(CM_GAMCOR_LUT_CONTROL, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
41
SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
42
SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
43
SRI(CM_GAMCOR_LUT_DATA, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
44
SRI(CM_GAMCOR_RAMB_START_CNTL_B, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
45
SRI(CM_GAMCOR_RAMB_START_CNTL_G, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
46
SRI(CM_GAMCOR_RAMB_START_CNTL_R, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
47
SRI(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
48
SRI(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
49
SRI(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
50
SRI(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
51
SRI(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
52
SRI(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
53
SRI(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
54
SRI(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
55
SRI(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
56
SRI(CM_GAMCOR_RAMB_REGION_0_1, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
57
SRI(CM_GAMCOR_RAMB_REGION_32_33, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
58
SRI(CM_GAMCOR_RAMB_OFFSET_B, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
59
SRI(CM_GAMCOR_RAMB_OFFSET_G, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
60
SRI(CM_GAMCOR_RAMB_OFFSET_R, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
61
SRI(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
62
SRI(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
63
SRI(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
64
SRI(CM_GAMCOR_RAMA_START_CNTL_B, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
65
SRI(CM_GAMCOR_RAMA_START_CNTL_G, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
66
SRI(CM_GAMCOR_RAMA_START_CNTL_R, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
67
SRI(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
68
SRI(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
69
SRI(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
70
SRI(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
71
SRI(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
72
SRI(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
73
SRI(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
74
SRI(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
75
SRI(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
76
SRI(CM_GAMCOR_RAMA_REGION_0_1, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
77
SRI(CM_GAMCOR_RAMA_REGION_32_33, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
78
SRI(CM_GAMCOR_RAMA_OFFSET_B, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
79
SRI(CM_GAMCOR_RAMA_OFFSET_G, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
80
SRI(CM_GAMCOR_RAMA_OFFSET_R, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
81
SRI(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
82
SRI(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
83
SRI(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
84
SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
85
SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
86
SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
87
SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
88
SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
89
SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
90
SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
91
SRI(CM_GAMUT_REMAP_B_C11_C12, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
92
SRI(CM_GAMUT_REMAP_B_C13_C14, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
93
SRI(CM_GAMUT_REMAP_B_C21_C22, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
94
SRI(CM_GAMUT_REMAP_B_C23_C24, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
95
SRI(CM_GAMUT_REMAP_B_C31_C32, CM, id),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
96
SRI(CM_GAMUT_REMAP_B_C33_C34, CM, id),\
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
424
SRI_ARR(CM_DEALPHA, CM, id), SRI_ARR(CM_MEM_PWR_STATUS, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
425
SRI_ARR(CM_BIAS_CR_R, CM, id), SRI_ARR(CM_BIAS_Y_G_CB_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
426
SRI_ARR(PRE_DEGAM, CNVC_CFG, id), SRI_ARR(CM_GAMCOR_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
427
SRI_ARR(CM_GAMCOR_LUT_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
428
SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
429
SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
430
SRI_ARR(CM_GAMCOR_LUT_DATA, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
431
SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
432
SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
433
SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
434
SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
435
SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
436
SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
437
SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
438
SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
439
SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
440
SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
441
SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
442
SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
443
SRI_ARR(CM_GAMCOR_RAMB_REGION_0_1, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
444
SRI_ARR(CM_GAMCOR_RAMB_REGION_32_33, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
445
SRI_ARR(CM_GAMCOR_RAMB_OFFSET_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
446
SRI_ARR(CM_GAMCOR_RAMB_OFFSET_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
447
SRI_ARR(CM_GAMCOR_RAMB_OFFSET_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
448
SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
449
SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
450
SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
451
SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
452
SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
453
SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
454
SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
455
SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
456
SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
457
SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
458
SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
459
SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
460
SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
461
SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
462
SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
463
SRI_ARR(CM_GAMCOR_RAMA_REGION_0_1, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
464
SRI_ARR(CM_GAMCOR_RAMA_REGION_32_33, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
465
SRI_ARR(CM_GAMCOR_RAMA_OFFSET_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
466
SRI_ARR(CM_GAMCOR_RAMA_OFFSET_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
467
SRI_ARR(CM_GAMCOR_RAMA_OFFSET_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
468
SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
469
SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
470
SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
471
SRI_ARR(CM_GAMUT_REMAP_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
472
SRI_ARR(CM_GAMUT_REMAP_C11_C12, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
473
SRI_ARR(CM_GAMUT_REMAP_C13_C14, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
474
SRI_ARR(CM_GAMUT_REMAP_C21_C22, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
475
SRI_ARR(CM_GAMUT_REMAP_C23_C24, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
476
SRI_ARR(CM_GAMUT_REMAP_C31_C32, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
477
SRI_ARR(CM_GAMUT_REMAP_C33_C34, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
478
SRI_ARR(CM_GAMUT_REMAP_B_C11_C12, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
479
SRI_ARR(CM_GAMUT_REMAP_B_C13_C14, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
480
SRI_ARR(CM_GAMUT_REMAP_B_C21_C22, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
481
SRI_ARR(CM_GAMUT_REMAP_B_C23_C24, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
482
SRI_ARR(CM_GAMUT_REMAP_B_C31_C32, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
483
SRI_ARR(CM_GAMUT_REMAP_B_C33_C34, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
509
SRI_ARR(CM_POST_CSC_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
510
SRI_ARR(CM_POST_CSC_C11_C12, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
511
SRI_ARR(CM_POST_CSC_C33_C34, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
512
SRI_ARR(CM_POST_CSC_B_C11_C12, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
513
SRI_ARR(CM_POST_CSC_B_C33_C34, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
514
SRI_ARR(CM_MEM_PWR_CTRL, CM, id), SRI_ARR(CM_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
515
SRI_ARR(CM_TEST_DEBUG_INDEX, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
516
SRI_ARR(CM_TEST_DEBUG_DATA, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
523
SRI_ARR(DPP_CONTROL, DPP_TOP, id), SRI_ARR(CM_HDR_MULT_COEF, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
237
SRI_ARR(CM_DEALPHA, CM, id), SRI_ARR(CM_MEM_PWR_STATUS, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
238
SRI_ARR(CM_BIAS_CR_R, CM, id), SRI_ARR(CM_BIAS_Y_G_CB_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
239
SRI_ARR(PRE_DEGAM, CNVC_CFG, id), SRI_ARR(CM_GAMCOR_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
240
SRI_ARR(CM_GAMCOR_LUT_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
241
SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
242
SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
243
SRI_ARR(CM_GAMCOR_LUT_DATA, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
244
SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
245
SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
246
SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
247
SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
248
SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
249
SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
250
SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
251
SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
252
SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
253
SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
254
SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
255
SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
256
SRI_ARR(CM_GAMCOR_RAMB_REGION_0_1, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
257
SRI_ARR(CM_GAMCOR_RAMB_REGION_32_33, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
258
SRI_ARR(CM_GAMCOR_RAMB_OFFSET_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
259
SRI_ARR(CM_GAMCOR_RAMB_OFFSET_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
260
SRI_ARR(CM_GAMCOR_RAMB_OFFSET_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
261
SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
262
SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
263
SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
264
SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
265
SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
266
SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
267
SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
268
SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
269
SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
270
SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
271
SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
272
SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
273
SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
274
SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
275
SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
276
SRI_ARR(CM_GAMCOR_RAMA_REGION_0_1, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
277
SRI_ARR(CM_GAMCOR_RAMA_REGION_32_33, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
278
SRI_ARR(CM_GAMCOR_RAMA_OFFSET_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
279
SRI_ARR(CM_GAMCOR_RAMA_OFFSET_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
280
SRI_ARR(CM_GAMCOR_RAMA_OFFSET_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
281
SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
282
SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
283
SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
308
SRI_ARR(CM_POST_CSC_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
309
SRI_ARR(CM_POST_CSC_C11_C12, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
310
SRI_ARR(CM_POST_CSC_C33_C34, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
311
SRI_ARR(CM_POST_CSC_B_C11_C12, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
312
SRI_ARR(CM_POST_CSC_B_C33_C34, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
313
SRI_ARR(CM_MEM_PWR_CTRL, CM, id), SRI_ARR(CM_CONTROL, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
314
SRI_ARR(CM_TEST_DEBUG_INDEX, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
315
SRI_ARR(CM_TEST_DEBUG_DATA, CM, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
336
SRI_ARR(DPP_CONTROL, DPP_TOP, id), SRI_ARR(CM_HDR_MULT_COEF, CM, id), \
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
346
phy_write(phy, CM(priv->cfg.cm), DPHY_CM);