drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1503

enum mpc_output_csc_mode ocsc_mode)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1522

enum mpc_output_csc_mode ocsc_mode)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1992

enum mpc_output_csc_mode ocsc_mode = params->set_output_csc_params.ocsc_mode;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2006

enum mpc_output_csc_mode ocsc_mode = params->set_ocsc_default_params.ocsc_mode;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

993

enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

134

enum mpc_output_csc_mode ocsc_mode;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

141

enum mpc_output_csc_mode ocsc_mode;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1638

struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1641

struct mpc *mpc, int opp_id, enum dc_color_space colorspace, enum mpc_output_csc_mode ocsc_mode);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

717

enum mpc_output_csc_mode ocsc_mode);

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

739

enum mpc_output_csc_mode ocsc_mode);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

135

enum mpc_output_csc_mode ocsc_mode)

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

189

enum mpc_output_csc_mode ocsc_mode)

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

296

enum mpc_output_csc_mode ocsc_mode);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.h

302

enum mpc_output_csc_mode ocsc_mode);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1307

enum mpc_output_csc_mode ocsc_mode)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1346

enum mpc_output_csc_mode ocsc_mode)

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1044

enum mpc_output_csc_mode ocsc_mode);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h

1050

enum mpc_output_csc_mode ocsc_mode);