drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

363

ADF_CSR_WR(csr, ADF_GEN6_ERRMSK3, ADF_GEN6_VFLNOTIFY);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

371

ADF_CSR_WR(addr, ADF_GEN6_SMIAPF_RP_X0_MASK_OFFSET, 0);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

372

ADF_CSR_WR(addr, ADF_GEN6_SMIAPF_RP_X1_MASK_OFFSET, 0);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

375

ADF_CSR_WR(addr, ADF_GEN6_SMIAPF_MASK_OFFSET, 0);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

411

ADF_CSR_WR(csr, ADF_GEN6_MSIX_RTTABLE_OFFSET(i), i);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

424

ADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETCTL(bank_number),

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

437

ADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETSTS(bank_number), ADF_WQM_CSR_RPRESETSTS_STATUS);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

587

ADF_CSR_WR(csr, ADF_GEN6_CSR_RINGMODECTL(bank_number), value);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

788

ADF_CSR_WR(addr, ADF_GEN6_ERRMSK2, csr);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

791

ADF_CSR_WR(addr, ADF_GEN6_PM_INTERRUPT, ADF_GEN6_PM_DRV_ACTIVE);

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

367

ADF_CSR_WR(csr_base, csr_low_offset, lower_32_bits(val)); \

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

368

ADF_CSR_WR(csr_base, csr_high_offset, upper_32_bits(val)); \

drivers/crypto/intel/qat/qat_common/adf_admin.c

132

ADF_CSR_WR(mailbox, mb_offset, 1);

drivers/crypto/intel/qat/qat_common/adf_admin.c

582

ADF_CSR_WR(pmisc_addr, adminmsg_u, upper_32_bits(reg_val));

drivers/crypto/intel/qat/qat_common/adf_admin.c

583

ADF_CSR_WR(pmisc_addr, adminmsg_l, lower_32_bits(reg_val));

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

40

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

47

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

49

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

54

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

57

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

60

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

64

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

66

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

70

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

73

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

77

ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

81

ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

111

ADF_CSR_WR(addr, ADF_GEN2_SMIAPF0_MASK_OFFSET, val);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

112

ADF_CSR_WR(addr, ADF_GEN2_SMIAPF1_MASK_OFFSET, ADF_GEN2_SMIA1_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

168

ADF_CSR_WR(pmisc_addr, ADF_SSMWDT(i), timer_val);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

170

ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKE(i), timer_val_pke);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

40

ADF_CSR_WR(pmisc_addr, ADF_GEN2_AE_CTX_ENABLES(i), val);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

43

ADF_CSR_WR(pmisc_addr, ADF_GEN2_AE_MISC_CONTROL(i), val);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

50

ADF_CSR_WR(pmisc_addr, ADF_GEN2_UERRSSMSH(i), val);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

53

ADF_CSR_WR(pmisc_addr, ADF_GEN2_CERRSSMSH(i), val);

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.h

22

ADF_CSR_WR(pmisc_bar_addr, AE2FUNCTION_MAP_A_OFFSET + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.h

28

ADF_CSR_WR(pmisc_bar_addr, AE2FUNCTION_MAP_B_OFFSET + \

drivers/crypto/intel/qat/qat_common/adf_gen2_pfvf.c

101

ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3);

drivers/crypto/intel/qat/qat_common/adf_gen2_pfvf.c

106

ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3);

drivers/crypto/intel/qat/qat_common/adf_gen2_pfvf.c

224

ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_msg | int_bit);

drivers/crypto/intel/qat/qat_common/adf_gen2_pfvf.c

255

ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val);

drivers/crypto/intel/qat/qat_common/adf_gen2_pfvf.c

319

ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val);

drivers/crypto/intel/qat/qat_common/adf_gen2_pfvf.c

60

ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val);

drivers/crypto/intel/qat/qat_common/adf_gen2_pfvf.c

69

ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

121

ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

125

ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

132

ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

139

ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

146

ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

150

ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

157

ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

164

ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

173

ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

182

ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

73

ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

81

ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

93

ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

96

ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

105

ADF_CSR_WR(addr, ADF_GEN4_SMIAPF_RP_X0_MASK_OFFSET, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

106

ADF_CSR_WR(addr, ADF_GEN4_SMIAPF_RP_X1_MASK_OFFSET, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

109

ADF_CSR_WR(addr, ADF_GEN4_SMIAPF_MASK_OFFSET, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

125

ADF_CSR_WR(addr, ADF_GEN4_ERRMSK2, csr);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

128

ADF_CSR_WR(addr, ADF_GEN4_PM_INTERRUPT, ADF_GEN4_PM_DRV_ACTIVE);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

176

ADF_CSR_WR(csr, ADF_GEN4_MSIX_RTTABLE_OFFSET(i), i);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

195

ADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETCTL(bank_number),

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

206

ADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETSTS(bank_number),

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

459

ADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETCTL(bank_number),

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

473

ADF_CSR_WR(csr, ADF_WQM_CSR_RPRESETSTS(bank_number),

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

94

ADF_CSR_WR(csr, ADF_GEN4_ERRMSK3, ADF_GEN4_VFLNOTIFY);

drivers/crypto/intel/qat/qat_common/adf_gen4_pfvf.c

128

ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val & ~ADF_PFVF_INT);

drivers/crypto/intel/qat/qat_common/adf_gen4_pfvf.c

43

ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, val);

drivers/crypto/intel/qat/qat_common/adf_gen4_pfvf.c

48

ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, ADF_GEN4_VF_MSK);

drivers/crypto/intel/qat/qat_common/adf_gen4_pfvf.c

75

ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, ADF_GEN4_VF_MSK);

drivers/crypto/intel/qat/qat_common/adf_gen4_pfvf.c

76

ADF_CSR_WR(pmisc_addr, ADF_4XXX_VM2PF_MSK, disabled | sources);

drivers/crypto/intel/qat/qat_common/adf_gen4_pfvf.c

96

ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val | ADF_PFVF_INT);

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.c

118

ADF_CSR_WR(pmisc, ADF_GEN4_ERRMSK2, val);

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.c

155

ADF_CSR_WR(pmisc, ADF_GEN4_PM_INTERRUPT, val);

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.c

160

ADF_CSR_WR(pmisc, ADF_GEN4_ERRMSK2, val);

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.c

50

ADF_CSR_WR(pmisc, ADF_GEN4_PM_HOST_MSG, msg);

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.c

88

ADF_CSR_WR(pmisc, ADF_GEN4_PM_INTERRUPT, pm_int_sts);

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.c

93

ADF_CSR_WR(pmisc, ADF_GEN4_ERRMSK2, val);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

102

ADF_CSR_WR(csr, ADF_GEN4_RI_MEM_PAR_ERR_EN0,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1041

ADF_CSR_WR(csr, ADF_GEN4_SSMCPPERR, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

107

ADF_CSR_WR(csr, ADF_GEN4_RIMISCCTL, ADF_GEN4_RIMISCSTS_BIT);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

110

ADF_CSR_WR(csr, ADF_GEN4_TI_CI_PAR_ERR_MASK, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1106

ADF_CSR_WR(csr, ADF_GEN4_SER_ERR_SSMSH, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

111

ADF_CSR_WR(csr, ADF_GEN4_TI_PULL0FUB_PAR_ERR_MASK, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

112

ADF_CSR_WR(csr, ADF_GEN4_TI_PUSHFUB_PAR_ERR_MASK, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

113

ADF_CSR_WR(csr, ADF_GEN4_TI_CD_PAR_ERR_MASK, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1130

ADF_CSR_WR(csr, ADF_GEN4_IAINTSTATSSM, iastatssm);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

114

ADF_CSR_WR(csr, ADF_GEN4_TI_TRNSB_PAR_ERR_MASK, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1149

ADF_CSR_WR(csr, ADF_GEN4_EXPRPSSMCPR, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

117

ADF_CSR_WR(csr, ADF_GEN4_RICPPINTCTL, ADF_GEN4_RICPPINTCTL_BITMASK);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1178

ADF_CSR_WR(csr, ADF_GEN4_EXPRPSSMXLT, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

119

ADF_CSR_WR(csr, ADF_GEN4_TICPPINTCTL, ADF_GEN4_TICPPINTCTL_BITMASK);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1210

ADF_CSR_WR(csr, ADF_GEN4_EXPRPSSMDCPR(i), reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1264

ADF_CSR_WR(csr, ADF_GEN4_CPP_CFC_ERR_STATUS_CLR,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

128

ADF_CSR_WR(csr, ADF_GEN4_TIMISCCTL, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

13

ADF_CSR_WR(csr, ADF_GEN4_ERRMSK0, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1312

ADF_CSR_WR(csr, ADF_GEN4_RICPPINTSTS, ricppintsts);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1333

ADF_CSR_WR(csr, ADF_GEN4_TICPPINTSTS, ticppintsts);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1356

ADF_CSR_WR(csr, ADF_GEN4_REG_ARAMCERR, aram_cerr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

136

ADF_CSR_WR(csr, ADF_GEN4_RI_MEM_PAR_ERR_EN0, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

139

ADF_CSR_WR(csr, ADF_GEN4_RIMISCCTL, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1393

ADF_CSR_WR(csr, ADF_GEN4_REG_ARAMUERR, aramuerr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

142

ADF_CSR_WR(csr, ADF_GEN4_TI_CI_PAR_ERR_MASK,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1429

ADF_CSR_WR(csr, ADF_GEN4_REG_CPPMEMTGTERR, cppmemtgterr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

144

ADF_CSR_WR(csr, ADF_GEN4_TI_PULL0FUB_PAR_ERR_MASK,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1455

ADF_CSR_WR(csr, ADF_GEN4_ATUFAULTSTATUS(i), atufaultstatus);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

146

ADF_CSR_WR(csr, ADF_GEN4_TI_PUSHFUB_PAR_ERR_MASK,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

148

ADF_CSR_WR(csr, ADF_GEN4_TI_CD_PAR_ERR_MASK,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

150

ADF_CSR_WR(csr, ADF_GEN4_TI_TRNSB_PAR_ERR_MASK,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

154

ADF_CSR_WR(csr, ADF_GEN4_RICPPINTCTL, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

156

ADF_CSR_WR(csr, ADF_GEN4_TICPPINTCTL, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

16

ADF_CSR_WR(csr, ADF_GEN4_ERRMSK1, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

164

ADF_CSR_WR(csr, ADF_GEN4_TIMISCCTL, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

173

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_SRC, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

174

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_ATH_CPH, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

175

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_CPR_XLT, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

176

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_DCPR_UCS, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

177

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_PKE, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

180

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_WAT_WCP, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

189

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_SRC,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

192

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_ATH_CPH,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

195

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_CPR_XLT,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

198

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_DCPR_UCS,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

201

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_PKE,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

205

ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITYMASK_WAT_WCP,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

216

ADF_CSR_WR(csr, ADF_GEN4_INTMASKSSM, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

22

ADF_CSR_WR(csr, ADF_GEN4_ERRMSK2,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

221

ADF_CSR_WR(csr, ADF_GEN4_SSMFEATREN, val);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

224

ADF_CSR_WR(csr, ADF_GEN4_SER_EN_SSMSH,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

228

ADF_CSR_WR(csr, ADF_GEN4_SPPPARERRMSK_ATH_CPH, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

229

ADF_CSR_WR(csr, ADF_GEN4_SPPPARERRMSK_CPR_XLT, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

230

ADF_CSR_WR(csr, ADF_GEN4_SPPPARERRMSK_DCPR_UCS, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

231

ADF_CSR_WR(csr, ADF_GEN4_SPPPARERRMSK_PKE, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

234

ADF_CSR_WR(csr, ADF_GEN4_SPPPARERRMSK_WAT_WCP, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

237

ADF_CSR_WR(csr, ADF_GEN4_SHINTMASKSSM_ATH_CPH, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

238

ADF_CSR_WR(csr, ADF_GEN4_SHINTMASKSSM_CPR_XLT, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

239

ADF_CSR_WR(csr, ADF_GEN4_SHINTMASKSSM_DCPR_UCS, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

240

ADF_CSR_WR(csr, ADF_GEN4_SHINTMASKSSM_PKE, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

243

ADF_CSR_WR(csr, ADF_GEN4_SHINTMASKSSM_WAT_WCP, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

253

ADF_CSR_WR(csr, ADF_GEN4_INTMASKSSM,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

259

ADF_CSR_WR(csr, ADF_GEN4_SSMFEATREN, val);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

262

ADF_CSR_WR(csr, ADF_GEN4_SER_EN_SSMSH, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

265

ADF_CSR_WR(csr, ADF_GEN4_SPPPARERRMSK_ATH_CPH,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

268

ADF_CSR_WR(csr, ADF_GEN4_SPPPARERRMSK_CPR_XLT,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

271

ADF_CSR_WR(csr, ADF_GEN4_SPPPARERRMSK_DCPR_UCS,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

274

ADF_CSR_WR(csr, ADF_GEN4_SPPPARERRMSK_PKE,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

278

ADF_CSR_WR(csr, ADF_GEN4_SPPPARERRMSK_WAT_WCP,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

282

ADF_CSR_WR(csr, ADF_GEN4_SHINTMASKSSM_ATH_CPH,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

285

ADF_CSR_WR(csr, ADF_GEN4_SHINTMASKSSM_CPR_XLT,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

288

ADF_CSR_WR(csr, ADF_GEN4_SHINTMASKSSM_DCPR_UCS,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

291

ADF_CSR_WR(csr, ADF_GEN4_SHINTMASKSSM_PKE,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

295

ADF_CSR_WR(csr, ADF_GEN4_SHINTMASKSSM_WAT_WCP,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

30

ADF_CSR_WR(csr, ADF_GEN4_ERRMSK3,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

301

ADF_CSR_WR(csr, ADF_GEN4_REG_ARAMCERRUERR_EN,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

304

ADF_CSR_WR(csr, ADF_GEN4_REG_ARAMCERR,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

307

ADF_CSR_WR(csr, ADF_GEN4_REG_ARAMUERR,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

310

ADF_CSR_WR(csr, ADF_GEN4_REG_CPPMEMTGTERR,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

316

ADF_CSR_WR(csr, ADF_GEN4_REG_ARAMCERRUERR_EN, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

317

ADF_CSR_WR(csr, ADF_GEN4_REG_ARAMCERR, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

318

ADF_CSR_WR(csr, ADF_GEN4_REG_ARAMUERR, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

319

ADF_CSR_WR(csr, ADF_GEN4_REG_CPPMEMTGTERR, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

364

ADF_CSR_WR(csr, ADF_GEN4_HIAECORERRLOG_CPP0, aecorrerr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

384

ADF_CSR_WR(csr, ADF_GEN4_HIAEUNCERRLOG_CPP0, aeuncorerr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

40

ADF_CSR_WR(csr, ADF_GEN4_ERRMSK0, ADF_GEN4_ERRSOU0_BIT);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

407

ADF_CSR_WR(csr, ADF_GEN4_HICPPAGENTCMDPARERRLOG, cmdparerr);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

43

ADF_CSR_WR(csr, ADF_GEN4_ERRMSK1, ADF_GEN4_ERRSOU1_BITMASK);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

440

ADF_CSR_WR(csr, ADF_GEN4_RIMEM_PARERR_STS, rimem_parerr_sts);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

459

ADF_CSR_WR(csr, ADF_GEN4_TI_CI_PAR_STS, ti_ci_par_sts);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

48

ADF_CSR_WR(csr, ADF_GEN4_ERRMSK2, val);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

481

ADF_CSR_WR(csr, ADF_GEN4_TI_PULL0FUB_PAR_STS,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

507

ADF_CSR_WR(csr, ADF_GEN4_TI_PUSHFUB_PAR_STS,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

51

ADF_CSR_WR(csr, ADF_GEN4_ERRMSK3, ADF_GEN4_ERRSOU3_BITMASK);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

531

ADF_CSR_WR(csr, ADF_GEN4_TI_CD_PAR_STS, ti_cd_par_sts);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

554

ADF_CSR_WR(csr, ADF_GEN4_TI_TRNSB_PAR_STS, ti_trnsb_par_sts);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

577

ADF_CSR_WR(csr, ADF_GEN4_RIMISCSTS, rimiscsts);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

60

ADF_CSR_WR(csr, ADF_GEN4_HIAECORERRLOGENABLE_CPP0, ae_mask);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

614

ADF_CSR_WR(csr, ADF_GEN4_UERRSSMSH, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

63

ADF_CSR_WR(csr, ADF_GEN4_HIAEUNCERRLOGENABLE_CPP0, ae_mask);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

636

ADF_CSR_WR(csr, ADF_GEN4_CERRSSMSH, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

658

ADF_CSR_WR(csr, ADF_GEN4_PPERR, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

69

ADF_CSR_WR(csr, ADF_GEN4_HIAECORERRLOGENABLE_CPP0, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

718

ADF_CSR_WR(csr, ADF_GEN4_SPPPULLCMDPARERR_ATH_CPH, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

72

ADF_CSR_WR(csr, ADF_GEN4_HIAEUNCERRLOGENABLE_CPP0, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

731

ADF_CSR_WR(csr, ADF_GEN4_SPPPULLCMDPARERR_CPR_XLT, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

744

ADF_CSR_WR(csr, ADF_GEN4_SPPPULLCMDPARERR_DCPR_UCS, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

757

ADF_CSR_WR(csr, ADF_GEN4_SPPPULLCMDPARERR_PKE, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

771

ADF_CSR_WR(csr, ADF_GEN4_SPPPULLCMDPARERR_WAT_WCP, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

794

ADF_CSR_WR(csr, ADF_GEN4_SPPPULLDATAPARERR_ATH_CPH, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

805

ADF_CSR_WR(csr, ADF_GEN4_SPPPULLDATAPARERR_CPR_XLT, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

81

ADF_CSR_WR(csr, ADF_GEN4_HICPPAGENTCMDPARERRLOGENABLE,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

816

ADF_CSR_WR(csr, ADF_GEN4_SPPPULLDATAPARERR_DCPR_UCS, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

827

ADF_CSR_WR(csr, ADF_GEN4_SPPPULLDATAPARERR_PKE, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

839

ADF_CSR_WR(csr, ADF_GEN4_SPPPULLDATAPARERR_WAT_WCP, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

84

ADF_CSR_WR(csr, ADF_GEN4_CPP_CFC_ERR_CTRL,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

861

ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHCMDPARERR_ATH_CPH, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

874

ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHCMDPARERR_CPR_XLT, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

887

ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHCMDPARERR_DCPR_UCS, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

901

ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHCMDPARERR_PKE, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

91

ADF_CSR_WR(csr, ADF_GEN4_HICPPAGENTCMDPARERRLOGENABLE, 0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

915

ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHCMDPARERR_WAT_WCP, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

93

ADF_CSR_WR(csr, ADF_GEN4_CPP_CFC_ERR_CTRL,

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

938

ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHDATAPARERR_ATH_CPH, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

949

ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHDATAPARERR_CPR_XLT, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

960

ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHDATAPARERR_DCPR_UCS, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

971

ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHDATAPARERR_PKE, reg);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

983

ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHDATAPARERR_WAT_WCP,

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

477

ADF_CSR_WR(csr, misc_states[i].ofs, regv);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

117

ADF_CSR_WR(csr, ADF_GEN6_ERRMSK0, ADF_GEN6_ERRSOU0_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

120

ADF_CSR_WR(csr, ADF_GEN6_ERRMSK1, ADF_GEN6_ERRMSK1_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

125

ADF_CSR_WR(csr, ADF_GEN6_ERRMSK2, val);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

128

ADF_CSR_WR(csr, ADF_GEN6_ERRMSK3, ADF_GEN6_ERRSOU3_DIS_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

13

ADF_CSR_WR(csr, ADF_GEN6_ERRMSK0, 0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

134

ADF_CSR_WR(csr, ADF_GEN6_HIAECORERRLOGENABLE_CPP0, 0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

137

ADF_CSR_WR(csr, ADF_GEN6_HIAEUNCERRLOGENABLE_CPP0, 0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

143

ADF_CSR_WR(csr, ADF_GEN6_HICPPAGENTCMDPARERRLOGENABLE, 0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

145

ADF_CSR_WR(csr, ADF_GEN6_CPP_CFC_ERR_CTRL, ADF_GEN6_CPP_CFC_ERR_CTRL_DIS_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

153

ADF_CSR_WR(csr, ADF_GEN6_RI_MEM_PAR_ERR_EN0, 0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

158

ADF_CSR_WR(csr, ADF_GEN6_RIMISCCTL, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

16

ADF_CSR_WR(csr, ADF_GEN6_ERRMSK1, 0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

161

ADF_CSR_WR(csr, ADF_GEN6_TI_CI_PAR_ERR_MASK, ADF_GEN6_TI_CI_PAR_STS_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

162

ADF_CSR_WR(csr, ADF_GEN6_TI_PULL0FUB_PAR_ERR_MASK, ADF_GEN6_TI_PULL0FUB_PAR_STS_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

163

ADF_CSR_WR(csr, ADF_GEN6_TI_PUSHFUB_PAR_ERR_MASK, ADF_GEN6_TI_PUSHFUB_PAR_STS_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

164

ADF_CSR_WR(csr, ADF_GEN6_TI_CD_PAR_ERR_MASK, ADF_GEN6_TI_CD_PAR_STS_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

165

ADF_CSR_WR(csr, ADF_GEN6_TI_TRNSB_PAR_ERR_MASK, ADF_GEN6_TI_TRNSB_PAR_STS_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

170

ADF_CSR_WR(csr, ADF_GEN6_RICPPINTCTL, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

174

ADF_CSR_WR(csr, ADF_GEN6_TICPPINTCTL, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

182

ADF_CSR_WR(csr, ADF_GEN6_TIMISCCTL, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

188

ADF_CSR_WR(csr, ADF_GEN6_INTMASKSSM, ADF_GEN6_INTMASKSSM_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

214

ADF_CSR_WR(csr, ADF_GEN6_HIAECORERRLOG_CPP0, ae);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

22

ADF_CSR_WR(csr, ADF_GEN6_ERRMSK2, ADF_GEN6_ERRSOU2_PM_INT_BIT);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

234

ADF_CSR_WR(csr, ADF_GEN6_HIAEUNCERRLOG_CPP0, ae);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

25

ADF_CSR_WR(csr, ADF_GEN6_ERRMSK3, 0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

252

ADF_CSR_WR(csr, ADF_GEN6_HICPPAGENTCMDPARERRLOG, cmd_par_err);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

279

ADF_CSR_WR(csr, ADF_GEN6_RIMEM_PARERR_STS, rimem_parerr_sts);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

290

ADF_CSR_WR(csr, ADF_GEN6_TI_CI_PAR_STS, ti_ci_par_sts);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

303

ADF_CSR_WR(csr, ADF_GEN6_TI_PULL0FUB_PAR_STS, ti_pullfub_par_sts);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

317

ADF_CSR_WR(csr, ADF_GEN6_TI_PUSHFUB_PAR_STS, ti_pushfub_par_sts);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

33

ADF_CSR_WR(csr, ADF_GEN6_HIAECORERRLOGENABLE_CPP0, ae_mask);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

330

ADF_CSR_WR(csr, ADF_GEN6_TI_CD_PAR_STS, ti_cd_par_sts);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

343

ADF_CSR_WR(csr, ADF_GEN6_TI_TRNSB_PAR_STS, ti_trnsb_par_sts);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

357

ADF_CSR_WR(csr, ADF_GEN6_RIMISCSTS, rimiscsts);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

36

ADF_CSR_WR(csr, ADF_GEN6_HIAEUNCERRLOGENABLE_CPP0, ae_mask);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

411

ADF_CSR_WR(csr, ADF_GEN6_CERRSSMSH, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

42

ADF_CSR_WR(csr, ADF_GEN6_HICPPAGENTCMDPARERRLOGENABLE,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

429

ADF_CSR_WR(csr, ADF_GEN6_UERRSSMSH, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

447

ADF_CSR_WR(csr, ADF_GEN6_PPERR, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

45

ADF_CSR_WR(csr, ADF_GEN6_CPP_CFC_ERR_CTRL, ADF_GEN6_CPP_CFC_ERR_CTRL_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

464

ADF_CSR_WR(csr, ADF_GEN6_SSM_FERR_STATUS, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

481

ADF_CSR_WR(csr, ADF_GEN6_SSM_FERR_STATUS, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

498

ADF_CSR_WR(csr, ADF_GEN6_SSM_FERR_STATUS, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

516

ADF_CSR_WR(csr, ADF_GEN6_SSM_FERR_STATUS, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

535

ADF_CSR_WR(csr, ADF_GEN6_IAINTSTATSSM, iastatssm);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

54

ADF_CSR_WR(csr, ADF_GEN6_RI_MEM_PAR_ERR_EN0, mask);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

57

ADF_CSR_WR(csr, ADF_GEN6_RIMISCCTL, ADF_GEN6_RIMISCSTS_BIT);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

571

ADF_CSR_WR(csr, ADF_GEN6_CPP_CFC_ERR_STATUS_CLR,

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

615

ADF_CSR_WR(csr, ADF_GEN6_RICPPINTSTS, ricppintsts);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

62

ADF_CSR_WR(csr, ADF_GEN6_TI_CI_PAR_ERR_MASK, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

632

ADF_CSR_WR(csr, ADF_GEN6_TICPPINTSTS, ticppintsts);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

654

ADF_CSR_WR(csr, ADF_GEN6_ATUFAULTSTATUS(i), atufaultstatus);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

66

ADF_CSR_WR(csr, ADF_GEN6_TI_PULL0FUB_PAR_ERR_MASK, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

672

ADF_CSR_WR(csr, ADF_GEN6_RLT_ERRLOG, rlterror);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

70

ADF_CSR_WR(csr, ADF_GEN6_TI_PUSHFUB_PAR_ERR_MASK, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

74

ADF_CSR_WR(csr, ADF_GEN6_TI_CD_PAR_ERR_MASK, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

78

ADF_CSR_WR(csr, ADF_GEN6_TI_TRNSB_PAR_ERR_MASK, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

81

ADF_CSR_WR(csr, ADF_GEN6_RICPPINTCTL, ADF_GEN6_RICPPINTCTL_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

82

ADF_CSR_WR(csr, ADF_GEN6_TICPPINTCTL, ADF_GEN6_TICPPINTCTL_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

91

ADF_CSR_WR(csr, ADF_GEN6_TIMISCCTL, reg);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

98

ADF_CSR_WR(csr, ADF_GEN6_INTMASKSSM, 0);

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

11

ADF_CSR_WR(csr_addr, (arb_offset) + \

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

15

ADF_CSR_WR(csr_addr, ((arb_offset) + (wt_offset)) + \

drivers/crypto/intel/qat/qat_common/adf_rl.c

1102

ADF_CSR_WR(pmisc_addr, rl_hw_data->pciin_tb_offset,

drivers/crypto/intel/qat/qat_common/adf_rl.c

1104

ADF_CSR_WR(pmisc_addr, rl_hw_data->pciout_tb_offset,

drivers/crypto/intel/qat/qat_common/adf_rl.c

275

ADF_CSR_WR(pmisc_addr, offset, node_id);

drivers/crypto/intel/qat/qat_common/adf_rl.c

290

ADF_CSR_WR(pmisc_addr, offset, parent_id);

drivers/crypto/intel/qat/qat_common/adf_rl.c

304

ADF_CSR_WR(pmisc_addr, offset, parent_id);

drivers/crypto/intel/qat/qat_common/adf_vf_isr.c

36

ADF_CSR_WR(pmisc_addr, ADF_VINTMSK_OFFSET, 0x0);

drivers/crypto/intel/qat/qat_common/adf_vf_isr.c

43

ADF_CSR_WR(pmisc_addr, ADF_VINTMSK_OFFSET, 0x2);

drivers/crypto/intel/qat/qat_common/icp_qat_hal.h

126

ADF_CSR_WR((handle)->hal_cap_g_ctl_csr_addr_v, csr, val)

drivers/crypto/intel/qat/qat_common/icp_qat_hal.h

133

ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)

drivers/crypto/intel/qat/qat_common/icp_qat_hal.h

140

ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val)

drivers/crypto/intel/qat/qat_common/icp_qat_hal.h

142

ADF_CSR_WR((handle)->hal_sram_addr_v, addr, val)

drivers/crypto/intel/qat/qat_common/qat_hal.c

459

ADF_CSR_WR(csr_addr, 0, csr_val);

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

129

ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val);

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

136

ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, val);

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

147

ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val);

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

152

ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, val);

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

191

ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3);

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

192

ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, errmsk5);

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

200

ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, errmsk3);

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

201

ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK5, errmsk5);