drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

428

ret = read_poll_timeout(ADF_CSR_RD, status,

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

584

value = ADF_CSR_RD(csr, ADF_GEN6_CSR_RINGMODECTL(bank_number));

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

786

csr = ADF_CSR_RD(addr, ADF_GEN6_ERRMSK2);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

794

ret = read_poll_timeout(ADF_CSR_RD, status,

drivers/crypto/intel/qat/qat_common/adf_admin.c

126

if (ADF_CSR_RD(mailbox, mb_offset) == 1) {

drivers/crypto/intel/qat/qat_common/adf_admin.c

134

ret = read_poll_timeout(ADF_CSR_RD, status, status == 0,

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

31

ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

34

ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h

37

ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

38

val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_AE_CTX_ENABLES(i));

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

41

val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_AE_MISC_CONTROL(i));

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

48

val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_UERRSSMSH(i));

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

51

val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_CERRSSMSH(i));

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.h

19

ADF_CSR_RD(pmisc_bar_addr, AE2FUNCTION_MAP_A_OFFSET + \

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.h

25

ADF_CSR_RD(pmisc_bar_addr, AE2FUNCTION_MAP_B_OFFSET + \

drivers/crypto/intel/qat/qat_common/adf_gen2_pfvf.c

216

csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset);

drivers/crypto/intel/qat/qat_common/adf_gen2_pfvf.c

227

ret = read_poll_timeout(ADF_CSR_RD, csr_val, !(csr_val & int_bit),

drivers/crypto/intel/qat/qat_common/adf_gen2_pfvf.c

287

csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset);

drivers/crypto/intel/qat/qat_common/adf_gen2_pfvf.c

58

u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3)

drivers/crypto/intel/qat/qat_common/adf_gen2_pfvf.c

67

u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3)

drivers/crypto/intel/qat/qat_common/adf_gen2_pfvf.c

78

errsou3 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRSOU3);

drivers/crypto/intel/qat/qat_common/adf_gen2_pfvf.c

85

errmsk3 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

109

l_base = ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) +

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

111

u_base = ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) +

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

129

ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

136

ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

143

ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

154

ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

161

ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

169

ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

178

ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

38

ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

42

ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

46

ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

49

ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

52

ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

55

ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

58

ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

61

ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

64

ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

67

ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

70

ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h

77

ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

123

csr = ADF_CSR_RD(addr, ADF_GEN4_ERRMSK2);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

131

ret = read_poll_timeout(ADF_CSR_RD, status,

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

199

ret = read_poll_timeout(ADF_CSR_RD, status,

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

443

ret = read_poll_timeout(ADF_CSR_RD, intsrc, intsrc,

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

462

return read_poll_timeout(ADF_CSR_RD, status,

drivers/crypto/intel/qat/qat_common/adf_gen4_pfvf.c

118

csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset);

drivers/crypto/intel/qat/qat_common/adf_gen4_pfvf.c

42

val = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_MSK) & ~vf_mask;

drivers/crypto/intel/qat/qat_common/adf_gen4_pfvf.c

56

sources = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_SOU);

drivers/crypto/intel/qat/qat_common/adf_gen4_pfvf.c

61

disabled = ADF_CSR_RD(pmisc_addr, ADF_4XXX_VM2PF_MSK);

drivers/crypto/intel/qat/qat_common/adf_gen4_pfvf.c

99

ret = read_poll_timeout(ADF_CSR_RD, csr_val, !(csr_val & ADF_PFVF_INT),

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.c

107

errmsk2 = ADF_CSR_RD(pmisc, ADF_GEN4_ERRMSK2);

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.c

111

errsou2 = ADF_CSR_RD(pmisc, ADF_GEN4_ERRSOU2);

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.c

116

val = ADF_CSR_RD(pmisc, ADF_GEN4_ERRMSK2);

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.c

120

val = ADF_CSR_RD(pmisc, ADF_GEN4_PM_INTERRUPT);

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.c

150

val = ADF_CSR_RD(pmisc, ADF_GEN4_PM_INTERRUPT);

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.c

158

val = ADF_CSR_RD(pmisc, ADF_GEN4_ERRMSK2);

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.c

31

msg = ADF_CSR_RD(pmisc, ADF_GEN4_PM_HOST_MSG);

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.c

53

return read_poll_timeout(ADF_CSR_RD, msg,

drivers/crypto/intel/qat/qat_common/adf_gen4_pm.c

91

val = ADF_CSR_RD(pmisc, ADF_GEN4_ERRMSK2);

drivers/crypto/intel/qat/qat_common/adf_gen4_pm_debugfs.c

181

val = ADF_CSR_RD(pmisc, ADF_GEN4_PM_HOST_MSG);

drivers/crypto/intel/qat/qat_common/adf_gen4_pm_debugfs.c

184

val = ADF_CSR_RD(pmisc, ADF_GEN4_PM_INTERRUPT);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1018

reg = ADF_CSR_RD(csr, ADF_GEN4_SSMCPPERR);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1070

reg = ADF_CSR_RD(csr, ADF_GEN4_SER_ERR_SSMSH);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1114

u32 iastatssm = ADF_CSR_RD(csr, ADF_GEN4_IAINTSTATSSM);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1138

u32 reg = ADF_CSR_RD(csr, ADF_GEN4_EXPRPSSMCPR);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1157

u32 reg = ADF_CSR_RD(csr, ADF_GEN4_EXPRPSSMXLT);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1190

reg = ADF_CSR_RD(csr, ADF_GEN4_EXPRPSSMDCPR(i));

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1241

reg = ADF_CSR_RD(csr, ADF_GEN4_CPP_CFC_ERR_STATUS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

125

reg = ADF_CSR_RD(csr, ADF_GEN4_TIMISCCTL);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1286

timiscsts = ADF_CSR_RD(csr, ADF_GEN4_TIMISCSTS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1304

ricppintsts = ADF_CSR_RD(csr, ADF_GEN4_RICPPINTSTS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1325

ticppintsts = ADF_CSR_RD(csr, ADF_GEN4_TICPPINTSTS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1346

aram_cerr = ADF_CSR_RD(csr, ADF_GEN4_REG_ARAMCERR);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1370

aramuerr = ADF_CSR_RD(csr, ADF_GEN4_REG_ARAMUERR);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1407

cppmemtgterr = ADF_CSR_RD(csr, ADF_GEN4_REG_CPPMEMTGTERR);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1444

u32 atufaultstatus = ADF_CSR_RD(csr, ADF_GEN4_ATUFAULTSTATUS(i));

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1480

u32 errsou = ADF_CSR_RD(csr, ADF_GEN4_ERRSOU0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1490

errsou = ADF_CSR_RD(csr, ADF_GEN4_ERRSOU1);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1496

errsou = ADF_CSR_RD(csr, ADF_GEN4_ERRSOU2);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

1502

errsou = ADF_CSR_RD(csr, ADF_GEN4_ERRSOU3);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

162

reg = ADF_CSR_RD(csr, ADF_GEN4_TIMISCCTL);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

219

val = ADF_CSR_RD(csr, ADF_GEN4_SSMFEATREN);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

257

val = ADF_CSR_RD(csr, ADF_GEN4_SSMFEATREN);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

353

u32 aecorrerr = ADF_CSR_RD(csr, ADF_GEN4_HIAECORERRLOG_CPP0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

375

aeuncorerr = ADF_CSR_RD(csr, ADF_GEN4_HIAEUNCERRLOG_CPP0);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

398

cmdparerr = ADF_CSR_RD(csr, ADF_GEN4_HICPPAGENTCMDPARERRLOG);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

421

rimem_parerr_sts = ADF_CSR_RD(csr, ADF_GEN4_RIMEM_PARERR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

453

ti_ci_par_sts = ADF_CSR_RD(csr, ADF_GEN4_TI_CI_PAR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

46

val = ADF_CSR_RD(csr, ADF_GEN4_ERRMSK2);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

474

ti_pullfub_par_sts = ADF_CSR_RD(csr, ADF_GEN4_TI_PULL0FUB_PAR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

498

ti_pushfub_par_sts = ADF_CSR_RD(csr, ADF_GEN4_TI_PUSHFUB_PAR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

522

ti_cd_par_sts = ADF_CSR_RD(csr, ADF_GEN4_TI_CD_PAR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

545

ti_trnsb_par_sts = ADF_CSR_RD(csr, ADF_GEN4_TI_TRNSB_PAR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

568

rimiscsts = ADF_CSR_RD(csr, ADF_GEN4_RIMISCSTS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

605

reg = ADF_CSR_RD(csr, ADF_GEN4_UERRSSMSH);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

627

reg = ADF_CSR_RD(csr, ADF_GEN4_CERRSSMSH);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

649

reg = ADF_CSR_RD(csr, ADF_GEN4_PPERR);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

667

u32 slice_hang_reg = ADF_CSR_RD(csr, slice_hang_offset);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

710

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPULLCMDPARERR_ATH_CPH);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

723

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPULLCMDPARERR_CPR_XLT);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

736

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPULLCMDPARERR_DCPR_UCS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

749

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPULLCMDPARERR_PKE);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

763

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPULLCMDPARERR_WAT_WCP);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

786

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPULLDATAPARERR_ATH_CPH);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

797

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPULLDATAPARERR_CPR_XLT);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

808

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPULLDATAPARERR_DCPR_UCS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

819

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPULLDATAPARERR_PKE);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

831

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPULLDATAPARERR_WAT_WCP);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

853

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPUSHCMDPARERR_ATH_CPH);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

866

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPUSHCMDPARERR_CPR_XLT);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

879

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPUSHCMDPARERR_DCPR_UCS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

892

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPUSHCMDPARERR_PKE);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

907

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPUSHCMDPARERR_WAT_WCP);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

930

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPUSHDATAPARERR_ATH_CPH);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

941

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPUSHDATAPARERR_CPR_XLT);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

952

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPUSHDATAPARERR_DCPR_UCS);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

963

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPUSHDATAPARERR_PKE);

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

975

reg = ADF_CSR_RD(csr, ADF_GEN4_SPPPUSHDATAPARERR_WAT_WCP);

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

711

regv = ADF_CSR_RD(csr, misc_states[i].offset);

drivers/crypto/intel/qat/qat_common/adf_gen6_pm_dbgfs.c

108

val = ADF_CSR_RD(pmisc, ADF_GEN6_PM_INTERRUPT);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

123

val = ADF_CSR_RD(csr, ADF_GEN6_ERRMSK2);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

156

reg = ADF_CSR_RD(csr, ADF_GEN6_RIMISCCTL);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

168

reg = ADF_CSR_RD(csr, ADF_GEN6_RICPPINTCTL);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

172

reg = ADF_CSR_RD(csr, ADF_GEN6_TICPPINTCTL);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

180

reg = ADF_CSR_RD(csr, ADF_GEN6_TIMISCCTL);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

206

ae = ADF_CSR_RD(csr, ADF_GEN6_HIAECORERRLOG_CPP0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

216

errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

229

ae = ADF_CSR_RD(csr, ADF_GEN6_HIAEUNCERRLOG_CPP0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

246

cmd_par_err = ADF_CSR_RD(csr, ADF_GEN6_HICPPAGENTCMDPARERRLOG);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

264

rimem_parerr_sts = ADF_CSR_RD(csr, ADF_GEN6_RIMEM_PARERR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

286

ti_ci_par_sts = ADF_CSR_RD(csr, ADF_GEN6_TI_CI_PAR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

299

ti_pullfub_par_sts = ADF_CSR_RD(csr, ADF_GEN6_TI_PULL0FUB_PAR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

312

ti_pushfub_par_sts = ADF_CSR_RD(csr, ADF_GEN6_TI_PUSHFUB_PAR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

325

ti_cd_par_sts = ADF_CSR_RD(csr, ADF_GEN6_TI_CD_PAR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

338

ti_trnsb_par_sts = ADF_CSR_RD(csr, ADF_GEN6_TI_TRNSB_PAR_STS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

351

rimiscsts = ADF_CSR_RD(csr, ADF_GEN6_RIMISCSTS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

396

errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU1);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

405

reg = ADF_CSR_RD(csr, ADF_GEN6_CERRSSMSH);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

423

reg = ADF_CSR_RD(csr, ADF_GEN6_UERRSSMSH);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

441

reg = ADF_CSR_RD(csr, ADF_GEN6_PPERR);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

459

reg = ADF_CSR_RD(csr, ADF_GEN6_SSM_FERR_STATUS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

476

reg = ADF_CSR_RD(csr, ADF_GEN6_SSM_FERR_STATUS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

493

reg = ADF_CSR_RD(csr, ADF_GEN6_SSM_FERR_STATUS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

510

reg = ADF_CSR_RD(csr, ADF_GEN6_SSM_FERR_STATUS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

522

u32 iastatssm = ADF_CSR_RD(csr, ADF_GEN6_IAINTSTATSSM);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

555

reg = ADF_CSR_RD(csr, ADF_GEN6_CPP_CFC_ERR_STATUS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

581

errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU2);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

594

timiscsts = ADF_CSR_RD(csr, ADF_GEN6_TIMISCSTS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

60

reg = ADF_CSR_RD(csr, ADF_GEN6_TI_CI_PAR_ERR_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

610

ricppintsts = ADF_CSR_RD(csr, ADF_GEN6_RICPPINTSTS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

627

ticppintsts = ADF_CSR_RD(csr, ADF_GEN6_TICPPINTSTS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

64

reg = ADF_CSR_RD(csr, ADF_GEN6_TI_PULL0FUB_PAR_ERR_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

647

atufaultstatus = ADF_CSR_RD(csr, ADF_GEN6_ATUFAULTSTATUS(i));

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

667

rlterror = ADF_CSR_RD(csr, ADF_GEN6_RLT_ERRLOG);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

68

reg = ADF_CSR_RD(csr, ADF_GEN6_TI_PUSHFUB_PAR_ERR_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

72

reg = ADF_CSR_RD(csr, ADF_GEN6_TI_CD_PAR_ERR_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

752

errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU3);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

76

reg = ADF_CSR_RD(csr, ADF_GEN6_TI_TRNSB_PAR_ERR_MASK);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

763

gensts = ADF_CSR_RD(csr, ADF_GEN6_GENSTS);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

783

errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU0);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

789

errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU1);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

795

errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU2);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

801

errsou = ADF_CSR_RD(csr, ADF_GEN6_ERRSOU3);

drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

88

reg = ADF_CSR_RD(csr, ADF_GEN6_TIMISCCTL);

drivers/crypto/intel/qat/qat_common/adf_vf_isr.c

144

v_int = ADF_CSR_RD(pmisc_bar_addr, ADF_VINTSOU_OFFSET);

drivers/crypto/intel/qat/qat_common/adf_vf_isr.c

147

v_mask = ADF_CSR_RD(pmisc_bar_addr, ADF_VINTMSK_OFFSET);

drivers/crypto/intel/qat/qat_common/icp_qat_hal.h

128

ADF_CSR_RD((handle)->hal_cap_g_ctl_csr_addr_v, csr)

drivers/crypto/intel/qat/qat_common/icp_qat_hal.h

134

#define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0)

drivers/crypto/intel/qat/qat_common/qat_hal.c

453

csr_val = ADF_CSR_RD(csr_addr, 0);

drivers/crypto/intel/qat/qat_common/qat_hal.c

457

csr_val = ADF_CSR_RD(csr_addr, 0);

drivers/crypto/intel/qat/qat_common/qat_hal.c

463

csr_val = ADF_CSR_RD(csr_addr, 0);

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

127

u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3)

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

134

u32 val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK5)

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

145

val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3)

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

150

val = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK5)

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

162

errsou3 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRSOU3);

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

163

errsou5 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRSOU5);

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

171

errmsk3 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK3);

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

172

errmsk5 = ADF_CSR_RD(pmisc_addr, ADF_GEN2_ERRMSK5);