arch/x86/events/intel/uncore.h

297

box->pmu->type->mmio_offset * box->pmu->pmu_idx;

arch/x86/events/intel/uncore.h

88

unsigned mmio_offset;

arch/x86/events/intel/uncore_snb.c

1722

.mmio_offset = 0,

arch/x86/events/intel/uncore_snbep.c

5133

.mmio_offset = SNR_IMC_MMIO_OFFSET,

arch/x86/events/intel/uncore_snbep.c

5661

box->pmu->type->mmio_offset * (box->pmu->pmu_idx % ICX_NUMBER_IMC_CHN);

arch/x86/events/intel/uncore_snbep.c

5692

.mmio_offset = SNR_IMC_MMIO_OFFSET,

drivers/gpu/drm/i915/display/intel_display_device.c

527

.mmio_offset = VLV_DISPLAY_BASE,

drivers/gpu/drm/i915/display/intel_display_device.c

648

.mmio_offset = VLV_DISPLAY_BASE,

drivers/gpu/drm/i915/display/intel_display_device.h

280

#define DISPLAY_MMIO_BASE(display) (DISPLAY_INFO((display))->mmio_offset)

drivers/gpu/drm/i915/display/intel_display_device.h

324

u32 mmio_offset;

drivers/gpu/drm/i915/gvt/firmware.c

241

memcpy(firmware->mmio, fw->data + h->mmio_offset,

drivers/gpu/drm/i915/gvt/firmware.c

48

u64 mmio_offset; /* offset in the file */

drivers/gpu/drm/i915/gvt/firmware.c

79

h->mmio_offset = h->cfg_space_offset + h->cfg_space_size;

drivers/gpu/drm/i915/gvt/firmware.c

87

p = firmware + h->mmio_offset;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

2099

gmu->mmio_offset = (u32)(start - res->start);

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

2258

gmu->mmio_offset = (u32)(start - res->start);

drivers/gpu/drm/msm/adreno/a6xx_gmu.h

135

#define GMU_BYTE_OFFSET(gmu, offset) (((offset) << 2) - (gmu)->mmio_offset)

drivers/gpu/drm/msm/adreno/a6xx_gmu.h

71

u32 mmio_offset;

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

1283

rcrtc->mmio_offset = mmio_offsets[hwindex];

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

38

return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

45

rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

52

rcar_du_write(rcdu, rcrtc->mmio_offset + reg,

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

53

rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

60

rcar_du_write(rcdu, rcrtc->mmio_offset + reg,

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

61

rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

69

rcar_du_write(rcdu, rcrtc->mmio_offset + DSYSR, rcrtc->dsysr);

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.h

53

unsigned int mmio_offset;

drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c

35

return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg);

drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c

40

rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);

drivers/gpu/drm/renesas/rcar-du/rcar_du_group.h

37

unsigned int mmio_offset;

drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c

906

rgrp->mmio_offset = mmio_offsets[i];

drivers/gpu/drm/renesas/rcar-du/rcar_du_plane.c

325

rcar_du_write(rgrp->dev, rgrp->mmio_offset + index * PLANE_OFF + reg,

drivers/net/wwan/iosm/iosm_ipc_mmio.h

83

struct mmio_offset offset;

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

1010

power_domain_info->perf_levels[level].mmio_offset +\

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

217

int mmio_offset;

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

361

pd_info->perf_levels[i].mmio_offset = pd_info->sst_header.pp_offset + offset;

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

817

power_domain_info->perf_levels[level].mmio_offset +\

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

830

power_domain_info->perf_levels[level].mmio_offset +\

include/uapi/drm/i915_drm.h

320

unsigned int mmio_offset;

include/uapi/drm/radeon_drm.h

586

unsigned long mmio_offset;

tools/include/uapi/drm/i915_drm.h

320

unsigned int mmio_offset;