arch/powerpc/kernel/udbg_16550.c

159

unsigned char __iomem *mmio_base;

arch/powerpc/kernel/udbg_16550.c

188

return in_8(udbg_uart.mmio_base + (reg * udbg_uart_stride));

arch/powerpc/kernel/udbg_16550.c

193

out_8(udbg_uart.mmio_base + (reg * udbg_uart_stride), data);

arch/powerpc/kernel/udbg_16550.c

201

udbg_uart.mmio_base = addr;

arch/x86/events/intel/uncore_snbep.c

6900

u64 mmio_base;

arch/x86/events/intel/uncore_snbep.c

6905

mmio_base = DMR_IMH1_HIOP_MMIO_BASE;

arch/x86/events/intel/uncore_snbep.c

6906

mmio_base += dmr_iio_freerunning_box_offsets[box->pmu->pmu_idx];

arch/x86/events/intel/uncore_snbep.c

6908

box->io_addr = ioremap(mmio_base, type->mmio_map_size);

arch/x86/kernel/cpu/microcode/intel.c

102

void __iomem *mmio_base;

arch/x86/kernel/cpu/microcode/intel.c

354

static inline u32 read_mbox_dword(void __iomem *mmio_base)

arch/x86/kernel/cpu/microcode/intel.c

356

u32 dword = readl(mmio_base + MBOX_RDDATA_OFFSET);

arch/x86/kernel/cpu/microcode/intel.c

359

writel(0, mmio_base + MBOX_RDDATA_OFFSET);

arch/x86/kernel/cpu/microcode/intel.c

363

static inline void write_mbox_dword(void __iomem *mmio_base, u32 dword)

arch/x86/kernel/cpu/microcode/intel.c

365

writel(dword, mmio_base + MBOX_WRDATA_OFFSET);

arch/x86/kernel/cpu/microcode/intel.c

368

static inline u64 read_mbox_header(void __iomem *mmio_base)

arch/x86/kernel/cpu/microcode/intel.c

372

low = read_mbox_dword(mmio_base);

arch/x86/kernel/cpu/microcode/intel.c

373

high = read_mbox_dword(mmio_base);

arch/x86/kernel/cpu/microcode/intel.c

378

static inline void write_mbox_header(void __iomem *mmio_base, u64 value)

arch/x86/kernel/cpu/microcode/intel.c

380

write_mbox_dword(mmio_base, value);

arch/x86/kernel/cpu/microcode/intel.c

381

write_mbox_dword(mmio_base, value >> 32);

arch/x86/kernel/cpu/microcode/intel.c

384

static void write_mbox_data(void __iomem *mmio_base, u32 *chunk, unsigned int chunk_bytes)

arch/x86/kernel/cpu/microcode/intel.c

394

write_mbox_dword(mmio_base, chunk[i]);

arch/x86/kernel/cpu/microcode/intel.c

410

writel(MASK_MBOX_CTRL_ABORT, ss->mmio_base + MBOX_CONTROL_OFFSET);

arch/x86/kernel/cpu/microcode/intel.c

477

status = readl(ss->mmio_base + MBOX_STATUS_OFFSET);

arch/x86/kernel/cpu/microcode/intel.c

515

write_mbox_header(ss->mmio_base, MBOX_HEADER(mbox_size));

arch/x86/kernel/cpu/microcode/intel.c

516

write_mbox_header(ss->mmio_base, MBOX_CMD_LOAD);

arch/x86/kernel/cpu/microcode/intel.c

517

write_mbox_data(ss->mmio_base, src_chunk, ss->chunk_size);

arch/x86/kernel/cpu/microcode/intel.c

521

writel(MASK_MBOX_CTRL_GO, ss->mmio_base + MBOX_CONTROL_OFFSET);

arch/x86/kernel/cpu/microcode/intel.c

542

header = read_mbox_header(ss->mmio_base);

arch/x86/kernel/cpu/microcode/intel.c

543

offset = read_mbox_dword(ss->mmio_base);

arch/x86/kernel/cpu/microcode/intel.c

544

status = read_mbox_dword(ss->mmio_base);

arch/x86/kernel/cpu/microcode/intel.c

580

ss.mmio_base = ioremap(mmio_pa, MBOX_REG_NUM * MBOX_REG_SIZE);

arch/x86/kernel/cpu/microcode/intel.c

581

if (WARN_ON_ONCE(!ss.mmio_base))

arch/x86/kernel/cpu/microcode/intel.c

601

iounmap(ss.mmio_base);

drivers/acpi/x86/lpss.c

1263

if (pdata->mmio_base &&

drivers/acpi/x86/lpss.c

1303

if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))

drivers/acpi/x86/lpss.c

135

val = readl(pdata->mmio_base + offset);

drivers/acpi/x86/lpss.c

136

writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);

drivers/acpi/x86/lpss.c

138

val = readl(pdata->mmio_base + LPSS_UART_CPR);

drivers/acpi/x86/lpss.c

141

val = readl(pdata->mmio_base + offset);

drivers/acpi/x86/lpss.c

143

writel(val, pdata->mmio_base + offset);

drivers/acpi/x86/lpss.c

153

val = readl(pdata->mmio_base + offset);

drivers/acpi/x86/lpss.c

155

writel(val, pdata->mmio_base + offset);

drivers/acpi/x86/lpss.c

194

if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))

drivers/acpi/x86/lpss.c

197

writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);

drivers/acpi/x86/lpss.c

426

if (!pdata->mmio_base

drivers/acpi/x86/lpss.c

431

prv_base = pdata->mmio_base + dev_desc->prv_offset;

drivers/acpi/x86/lpss.c

641

pdata->mmio_base = ioremap(rentry->res->start, pdata->mmio_size);

drivers/acpi/x86/lpss.c

646

if (!pdata->mmio_base) {

drivers/acpi/x86/lpss.c

692

return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);

drivers/acpi/x86/lpss.c

698

writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);

drivers/acpi/x86/lpss.c

717

if (WARN_ON(!pdata || !pdata->mmio_base)) {

drivers/acpi/x86/lpss.c

97

void __iomem *mmio_base;

drivers/ata/pata_pdc2027x.c

461

void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];

drivers/ata/pata_pdc2027x.c

467

bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;

drivers/ata/pata_pdc2027x.c

468

bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;

drivers/ata/pata_pdc2027x.c

471

bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;

drivers/ata/pata_pdc2027x.c

472

bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;

drivers/ata/pata_pdc2027x.c

502

void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];

drivers/ata/pata_pdc2027x.c

521

pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);

drivers/ata/pata_pdc2027x.c

560

iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL);

drivers/ata/pata_pdc2027x.c

561

ioread16(mmio_base + PDC_PLL_CTL); /* flush */

drivers/ata/pata_pdc2027x.c

570

pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);

drivers/ata/pata_pdc2027x.c

585

void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];

drivers/ata/pata_pdc2027x.c

592

scr = ioread32(mmio_base + PDC_SYS_CTL);

drivers/ata/pata_pdc2027x.c

594

iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);

drivers/ata/pata_pdc2027x.c

595

ioread32(mmio_base + PDC_SYS_CTL); /* flush */

drivers/ata/pata_pdc2027x.c

609

scr = ioread32(mmio_base + PDC_SYS_CTL);

drivers/ata/pata_pdc2027x.c

611

iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);

drivers/ata/pata_pdc2027x.c

612

ioread32(mmio_base + PDC_SYS_CTL); /* flush */

drivers/ata/pata_pdc2027x.c

690

void __iomem *mmio_base;

drivers/ata/pata_pdc2027x.c

714

mmio_base = host->iomap[PDC_MMIO_BAR];

drivers/ata/pata_pdc2027x.c

719

pdc_ata_setup_port(&ap->ioaddr, mmio_base + cmd_offset[i]);

drivers/ata/pata_pdc2027x.c

720

ap->ioaddr.bmdma_addr = mmio_base + bmdma_offset[i];

drivers/ata/pata_sil680.c

340

void __iomem *mmio_base;

drivers/ata/pata_sil680.c

380

mmio_base = host->iomap[SIL680_MMIO_BAR];

drivers/ata/pata_sil680.c

381

host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00;

drivers/ata/pata_sil680.c

382

host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80;

drivers/ata/pata_sil680.c

383

host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a;

drivers/ata/pata_sil680.c

384

host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a;

drivers/ata/pata_sil680.c

386

host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08;

drivers/ata/pata_sil680.c

387

host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0;

drivers/ata/pata_sil680.c

388

host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca;

drivers/ata/pata_sil680.c

389

host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca;

drivers/ata/pdc_adma.c

553

void __iomem *mmio_base;

drivers/ata/pdc_adma.c

575

mmio_base = host->iomap[ADMA_MMIO_BAR];

drivers/ata/pdc_adma.c

585

void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);

drivers/ata/pdc_adma.c

586

unsigned int offset = port_base - mmio_base;

drivers/ata/sata_inic162x.c

234

void __iomem *mmio_base;

drivers/ata/sata_inic162x.c

268

return hpriv->mmio_base + ap->port_no * PORT_SIZE;

drivers/ata/sata_inic162x.c

426

host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT);

drivers/ata/sata_inic162x.c

752

static int init_controller(void __iomem *mmio_base, u16 hctl)

drivers/ata/sata_inic162x.c

762

writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL);

drivers/ata/sata_inic162x.c

763

readw(mmio_base + HOST_CTL); /* flush */

drivers/ata/sata_inic162x.c

767

val = readw(mmio_base + HOST_CTL);

drivers/ata/sata_inic162x.c

777

void __iomem *port_base = mmio_base + i * PORT_SIZE;

drivers/ata/sata_inic162x.c

784

writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL);

drivers/ata/sata_inic162x.c

785

val = readw(mmio_base + HOST_IRQ_MASK);

drivers/ata/sata_inic162x.c

787

writew(val, mmio_base + HOST_IRQ_MASK);

drivers/ata/sata_inic162x.c

804

rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);

drivers/ata/sata_inic162x.c

852

hpriv->mmio_base = iomap[mmio_bar];

drivers/ata/sata_inic162x.c

853

hpriv->cached_hctl = readw(hpriv->mmio_base + HOST_CTL);

drivers/ata/sata_inic162x.c

869

rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);

drivers/ata/sata_mv.c

1254

static void mv_dump_all_regs(void __iomem *mmio_base,

drivers/ata/sata_mv.c

1272

mv_dump_mem(&pdev->dev, mmio_base+0xc00, 0x3c);

drivers/ata/sata_mv.c

1273

mv_dump_mem(&pdev->dev, mmio_base+0xd00, 0x34);

drivers/ata/sata_mv.c

1274

mv_dump_mem(&pdev->dev, mmio_base+0xf00, 0x4);

drivers/ata/sata_mv.c

1275

mv_dump_mem(&pdev->dev, mmio_base+0x1d00, 0x6c);

drivers/ata/sata_mv.c

1277

hc_base = mv_hc_base(mmio_base, hc);

drivers/ata/sata_mv.c

1282

port_base = mv_port_base(mmio_base, p);

drivers/ata/sata_nv.c

1580

void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];

drivers/ata/sata_nv.c

1584

mask = readb(mmio_base + NV_INT_ENABLE_CK804);

drivers/ata/sata_nv.c

1586

writeb(mask, mmio_base + NV_INT_ENABLE_CK804);

drivers/ata/sata_nv.c

1591

void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];

drivers/ata/sata_nv.c

1595

writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);

drivers/ata/sata_nv.c

1597

mask = readb(mmio_base + NV_INT_ENABLE_CK804);

drivers/ata/sata_nv.c

1599

writeb(mask, mmio_base + NV_INT_ENABLE_CK804);

drivers/ata/sata_nv.c

1604

void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];

drivers/ata/sata_nv.c

1608

writel(NV_INT_ALL_MCP55 << shift, mmio_base + NV_INT_STATUS_MCP55);

drivers/ata/sata_nv.c

1610

mask = readl(mmio_base + NV_INT_ENABLE_MCP55);

drivers/ata/sata_nv.c

1612

writel(mask, mmio_base + NV_INT_ENABLE_MCP55);

drivers/ata/sata_nv.c

1617

void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];

drivers/ata/sata_nv.c

1621

writel(NV_INT_ALL_MCP55 << shift, mmio_base + NV_INT_STATUS_MCP55);

drivers/ata/sata_nv.c

1623

mask = readl(mmio_base + NV_INT_ENABLE_MCP55);

drivers/ata/sata_nv.c

1625

writel(mask, mmio_base + NV_INT_ENABLE_MCP55);

drivers/ata/sata_qstor.c

192

u8 __iomem *mmio_base = qs_mmio_base(ap->host);

drivers/ata/sata_qstor.c

194

writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */

drivers/ata/sata_qstor.c

200

u8 __iomem *mmio_base = qs_mmio_base(ap->host);

drivers/ata/sata_qstor.c

203

writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */

drivers/ata/sata_qstor.c

354

u8 __iomem *mmio_base = qs_mmio_base(host);

drivers/ata/sata_qstor.c

357

u32 sff0 = readl(mmio_base + QS_HST_SFF);

drivers/ata/sata_qstor.c

358

u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);

drivers/ata/sata_qstor.c

460

void __iomem *mmio_base = qs_mmio_base(ap->host);

drivers/ata/sata_qstor.c

461

void __iomem *chan = mmio_base + (ap->port_no * 0x4000);

drivers/ata/sata_qstor.c

482

void __iomem *mmio_base = qs_mmio_base(host);

drivers/ata/sata_qstor.c

484

writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */

drivers/ata/sata_qstor.c

485

writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */

drivers/ata/sata_qstor.c

490

void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];

drivers/ata/sata_qstor.c

493

writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */

drivers/ata/sata_qstor.c

494

writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */

drivers/ata/sata_qstor.c

498

u8 __iomem *chan = mmio_base + (port_no * 0x4000);

drivers/ata/sata_qstor.c

503

writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */

drivers/ata/sata_qstor.c

506

u8 __iomem *chan = mmio_base + (port_no * 0x4000);

drivers/ata/sata_qstor.c

515

writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */

drivers/ata/sata_qstor.c

528

static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)

drivers/ata/sata_qstor.c

530

u32 bus_info = readl(mmio_base + QS_HID_HPHY);

drivers/ata/sata_sil.c

254

void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];

drivers/ata/sata_sil.c

255

void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2;

drivers/ata/sata_sil.c

280

void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];

drivers/ata/sata_sil.c

281

void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2;

drivers/ata/sata_sil.c

348

void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];

drivers/ata/sata_sil.c

349

void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode;

drivers/ata/sata_sil.c

509

void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];

drivers/ata/sata_sil.c

517

u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);

drivers/ata/sata_sil.c

538

void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];

drivers/ata/sata_sil.c

542

writel(0, mmio_base + sil_port[ap->port_no].sien);

drivers/ata/sata_sil.c

545

tmp = readl(mmio_base + SIL_SYSCFG);

drivers/ata/sata_sil.c

547

writel(tmp, mmio_base + SIL_SYSCFG);

drivers/ata/sata_sil.c

548

readl(mmio_base + SIL_SYSCFG); /* flush */

drivers/ata/sata_sil.c

566

void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];

drivers/ata/sata_sil.c

575

writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);

drivers/ata/sata_sil.c

578

tmp = readl(mmio_base + SIL_SYSCFG);

drivers/ata/sata_sil.c

580

writel(tmp, mmio_base + SIL_SYSCFG);

drivers/ata/sata_sil.c

653

void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];

drivers/ata/sata_sil.c

665

mmio_base + sil_port[i].fifo_cfg);

drivers/ata/sata_sil.c

675

tmp = readl(mmio_base + sil_port[i].sfis_cfg);

drivers/ata/sata_sil.c

681

writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);

drivers/ata/sata_sil.c

688

tmp = readl(mmio_base + sil_port[2].bmdma);

drivers/ata/sata_sil.c

691

mmio_base + sil_port[2].bmdma);

drivers/ata/sata_sil.c

727

void __iomem *mmio_base;

drivers/ata/sata_sil.c

765

mmio_base = host->iomap[SIL_MMIO_BAR];

drivers/ata/sata_sil.c

771

ioaddr->cmd_addr = mmio_base + sil_port[i].tf;

drivers/ata/sata_sil.c

773

ioaddr->ctl_addr = mmio_base + sil_port[i].ctl;

drivers/ata/sata_sil.c

774

ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma;

drivers/ata/sata_sil.c

775

ioaddr->scr_addr = mmio_base + sil_port[i].scr;

drivers/ata/sata_svw.c

416

void __iomem *mmio_base;

drivers/ata/sata_svw.c

461

mmio_base = host->iomap[bar_pos];

drivers/ata/sata_svw.c

470

k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);

drivers/ata/sata_svw.c

484

writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,

drivers/ata/sata_svw.c

485

mmio_base + K2_SATA_SICR1_OFFSET);

drivers/ata/sata_svw.c

488

writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);

drivers/ata/sata_svw.c

489

writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);

drivers/ata/sata_sx4.c

747

void __iomem *mmio_base;

drivers/ata/sata_sx4.c

752

mmio_base = host->iomap[PDC_MMIO_BAR];

drivers/ata/sata_sx4.c

755

mmio_base += PDC_CHIP0_OFS;

drivers/ata/sata_sx4.c

756

mask = readl(mmio_base + PDC_20621_SEQMASK);

drivers/ata/sata_sx4.c

784

mmio_base);

drivers/ata/sata_vsc.c

332

void __iomem *mmio_base;

drivers/ata/sata_vsc.c

359

mmio_base = host->iomap[VSC_MMIO_BAR];

drivers/ata/sata_vsc.c

365

vsc_sata_setup_port(&ap->ioaddr, mmio_base + offset);

drivers/clk/mmp/clk-audio.c

125

aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0);

drivers/clk/mmp/clk-audio.c

133

aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1);

drivers/clk/mmp/clk-audio.c

218

writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL0);

drivers/clk/mmp/clk-audio.c

222

writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL1);

drivers/clk/mmp/clk-audio.c

259

priv->sspa_mux.reg = priv->mmio_base + SSPA_AUD_CTRL;

drivers/clk/mmp/clk-audio.c

269

priv->sysclk_div.reg = priv->mmio_base + SSPA_AUD_CTRL;

drivers/clk/mmp/clk-audio.c

282

priv->sysclk_gate.reg = priv->mmio_base + SSPA_AUD_CTRL;

drivers/clk/mmp/clk-audio.c

290

priv->sspa0_div.reg = priv->mmio_base + SSPA_AUD_CTRL;

drivers/clk/mmp/clk-audio.c

303

priv->sspa0_gate.reg = priv->mmio_base + SSPA_AUD_CTRL;

drivers/clk/mmp/clk-audio.c

312

priv->sspa1_mux.reg = priv->mmio_base + SSPA_AUD_CTRL;

drivers/clk/mmp/clk-audio.c

321

priv->sspa1_div.reg = priv->mmio_base + SSPA_AUD_CTRL;

drivers/clk/mmp/clk-audio.c

334

priv->sspa1_gate.reg = priv->mmio_base + SSPA_AUD_CTRL;

drivers/clk/mmp/clk-audio.c

364

priv->mmio_base = devm_platform_ioremap_resource(pdev, 0);

drivers/clk/mmp/clk-audio.c

365

if (IS_ERR(priv->mmio_base))

drivers/clk/mmp/clk-audio.c

366

return PTR_ERR(priv->mmio_base);

drivers/clk/mmp/clk-audio.c

402

priv->aud_ctrl = readl(priv->mmio_base + SSPA_AUD_CTRL);

drivers/clk/mmp/clk-audio.c

403

priv->aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0);

drivers/clk/mmp/clk-audio.c

404

priv->aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1);

drivers/clk/mmp/clk-audio.c

415

writel(priv->aud_ctrl, priv->mmio_base + SSPA_AUD_CTRL);

drivers/clk/mmp/clk-audio.c

416

writel(priv->aud_pll_ctrl0, priv->mmio_base + SSPA_AUD_PLL_CTRL0);

drivers/clk/mmp/clk-audio.c

417

writel(priv->aud_pll_ctrl1, priv->mmio_base + SSPA_AUD_PLL_CTRL1);

drivers/clk/mmp/clk-audio.c

61

void __iomem *mmio_base;

drivers/counter/ti-ecap-capture.c

473

void __iomem *mmio_base;

drivers/counter/ti-ecap-capture.c

503

mmio_base = devm_platform_ioremap_resource(pdev, 0);

drivers/counter/ti-ecap-capture.c

504

if (IS_ERR(mmio_base))

drivers/counter/ti-ecap-capture.c

505

return PTR_ERR(mmio_base);

drivers/counter/ti-ecap-capture.c

507

ecap_dev->regmap = devm_regmap_init_mmio(dev, mmio_base, &ecap_cnt_regmap_config);

drivers/edac/al_mc_edac.c

128

eccerrcnt = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_ERR_COUNT);

drivers/edac/al_mc_edac.c

133

eccuaddr0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_ADDR0);

drivers/edac/al_mc_edac.c

134

eccuaddr1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_ADDR1);

drivers/edac/al_mc_edac.c

135

eccusyn0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_SYND0);

drivers/edac/al_mc_edac.c

136

eccusyn1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_SYND1);

drivers/edac/al_mc_edac.c

137

eccusyn2 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_SYND2);

drivers/edac/al_mc_edac.c

140

al_mc->mmio_base + AL_MC_ECC_CLEAR);

drivers/edac/al_mc_edac.c

195

static enum scrub_type get_scrub_mode(void __iomem *mmio_base)

drivers/edac/al_mc_edac.c

199

ecccfg0 = readl(mmio_base + AL_MC_ECC_CFG);

drivers/edac/al_mc_edac.c

222

void __iomem *mmio_base;

drivers/edac/al_mc_edac.c

226

mmio_base = devm_platform_ioremap_resource(pdev, 0);

drivers/edac/al_mc_edac.c

227

if (IS_ERR(mmio_base)) {

drivers/edac/al_mc_edac.c

229

PTR_ERR(mmio_base));

drivers/edac/al_mc_edac.c

230

return PTR_ERR(mmio_base);

drivers/edac/al_mc_edac.c

248

al_mc->mmio_base = mmio_base;

drivers/edac/al_mc_edac.c

281

mci->scrub_mode = get_scrub_mode(mmio_base);

drivers/edac/al_mc_edac.c

57

void __iomem *mmio_base;

drivers/edac/al_mc_edac.c

83

eccerrcnt = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_ERR_COUNT);

drivers/edac/al_mc_edac.c

88

ecccaddr0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_ADDR0);

drivers/edac/al_mc_edac.c

89

ecccaddr1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_ADDR1);

drivers/edac/al_mc_edac.c

90

ecccsyn0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND0);

drivers/edac/al_mc_edac.c

91

ecccsyn1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND1);

drivers/edac/al_mc_edac.c

92

ecccsyn2 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND2);

drivers/edac/al_mc_edac.c

95

al_mc->mmio_base + AL_MC_ECC_CLEAR);

drivers/edac/imh_base.c

264

DEFINE_LOCAL_REG(reg, cfg, i, true, ubox, 0, mmio_base);

drivers/edac/imh_base.c

278

DEFINE_LOCAL_REG(reg2, cfg, i, false, ubox, 0, mmio_base);

drivers/gpu/drm/i915/display/intel_display_core.h

394

u32 mmio_base;

drivers/gpu/drm/i915/display/intel_display_core.h

431

u32 mmio_base;

drivers/gpu/drm/i915/display/intel_display_core.h

544

u32 mmio_base;

drivers/gpu/drm/i915/display/intel_gmbus.c

911

display->gmbus.mmio_base = VLV_DISPLAY_BASE;

drivers/gpu/drm/i915/display/intel_gmbus.c

917

display->gmbus.mmio_base = PCH_DISPLAY_BASE;

drivers/gpu/drm/i915/display/intel_gmbus_regs.h

11

#define __GMBUS_MMIO_BASE(__display) ((__display)->gmbus.mmio_base)

drivers/gpu/drm/i915/display/intel_pps.c

1776

display->pps.mmio_base = PCH_PPS_BASE;

drivers/gpu/drm/i915/display/intel_pps.c

1778

display->pps.mmio_base = VLV_PPS_BASE;

drivers/gpu/drm/i915/display/intel_pps.c

1780

display->pps.mmio_base = PPS_BASE;

drivers/gpu/drm/i915/display/intel_pps_regs.h

17

_MMIO((display)->pps.mmio_base - PPS_BASE + (reg) + (pps_idx) * 0x100)

drivers/gpu/drm/i915/display/vlv_dsi.c

1918

display->dsi.mmio_base = BXT_MIPI_BASE;

drivers/gpu/drm/i915/display/vlv_dsi.c

1920

display->dsi.mmio_base = VLV_MIPI_BASE;

drivers/gpu/drm/i915/display/vlv_dsi_regs.h

14

#define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base)

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

166

*cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base));

drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c

1618

const u32 GPR0 = engine->mmio_base + 0x600;

drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c

1653

const u32 reg = engine->mmio_base + 0x420;

drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c

926

*cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(engine->mmio_base));

drivers/gpu/drm/i915/gt/intel_engine.h

59

__ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base))

drivers/gpu/drm/i915/gt/intel_engine.h

69

lower_reg__((engine__)->mmio_base), \

drivers/gpu/drm/i915/gt/intel_engine.h

70

upper_reg__((engine__)->mmio_base))

drivers/gpu/drm/i915/gt/intel_engine.h

73

__ENGINE_REG_OP(read, (engine__), reg__((engine__)->mmio_base, (idx__)))

drivers/gpu/drm/i915/gt/intel_engine.h

76

__ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base), (val__))

drivers/gpu/drm/i915/gt/intel_engine_cs.c

1628

const i915_reg_t mode = RING_MI_MODE(engine->mmio_base);

drivers/gpu/drm/i915/gt/intel_engine_cs.c

1638

intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),

drivers/gpu/drm/i915/gt/intel_engine_cs.c

1773

u32 mmio_base = engine->mmio_base;

drivers/gpu/drm/i915/gt/intel_engine_cs.c

1782

intel_uncore_read(uncore, RING_INSTDONE(mmio_base));

drivers/gpu/drm/i915/gt/intel_engine_cs.c

1816

intel_uncore_read(uncore, RING_INSTDONE(mmio_base));

drivers/gpu/drm/i915/gt/intel_engine_cs.c

1829

intel_uncore_read(uncore, RING_INSTDONE(mmio_base));

drivers/gpu/drm/i915/gt/intel_engine_cs.c

1843

if (I915_SELFTEST_ONLY(!engine->mmio_base))

drivers/gpu/drm/i915/gt/intel_engine_cs.c

2417

drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base);

drivers/gpu/drm/i915/gt/intel_engine_cs.c

491

engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);

drivers/gpu/drm/i915/gt/intel_engine_types.h

394

u32 mmio_base;

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

1775

_MMIO(engine->mmio_base + status));

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

2753

u32 base = engine->mmio_base;

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

3538

u32 base = engine->mmio_base;

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

3561

RING_EXECLIST_CONTROL(engine->mmio_base),

drivers/gpu/drm/i915/gt/intel_lrc.c

62

const u32 base = engine->mmio_base;

drivers/gpu/drm/i915/gt/intel_rc6.c

161

intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);

drivers/gpu/drm/i915/gt/intel_rc6.c

219

intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);

drivers/gpu/drm/i915/gt/intel_rc6.c

246

intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);

drivers/gpu/drm/i915/gt/intel_rc6.c

371

intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);

drivers/gpu/drm/i915/gt/intel_rc6.c

398

intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);

drivers/gpu/drm/i915/gt/intel_rc6.c

79

intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);

drivers/gpu/drm/i915/gt/intel_reset.c

382

sfc_lock->lock_reg = GEN11_VCS_SFC_FORCED_LOCK(engine->mmio_base);

drivers/gpu/drm/i915/gt/intel_reset.c

385

sfc_lock->ack_reg = GEN11_VCS_SFC_LOCK_STATUS(engine->mmio_base);

drivers/gpu/drm/i915/gt/intel_reset.c

388

sfc_lock->usage_reg = GEN11_VCS_SFC_LOCK_STATUS(engine->mmio_base);

drivers/gpu/drm/i915/gt/intel_reset.c

394

sfc_lock->lock_reg = GEN11_VECS_SFC_FORCED_LOCK(engine->mmio_base);

drivers/gpu/drm/i915/gt/intel_reset.c

397

sfc_lock->ack_reg = GEN11_VECS_SFC_LOCK_ACK(engine->mmio_base);

drivers/gpu/drm/i915/gt/intel_reset.c

400

sfc_lock->usage_reg = GEN11_VECS_SFC_USAGE(engine->mmio_base);

drivers/gpu/drm/i915/gt/intel_reset.c

447

GEN12_HCP_SFC_LOCK_STATUS(engine->mmio_base)) &

drivers/gpu/drm/i915/gt/intel_reset.c

563

const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);

drivers/gpu/drm/i915/gt/intel_reset.c

604

RING_RESET_CTL(engine->mmio_base),

drivers/gpu/drm/i915/gt/intel_ring_submission.c

109

hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);

drivers/gpu/drm/i915/gt/intel_ring_submission.c

111

hwsp = RING_HWS_PGA(engine->mmio_base);

drivers/gpu/drm/i915/gt/intel_ring_submission.c

132

RING_INSTPM(engine->mmio_base),

drivers/gpu/drm/i915/gt/intel_ring_submission.c

268

RING_CTL(engine->mmio_base),

drivers/gpu/drm/i915/gt/intel_ring_submission.c

705

*cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));

drivers/gpu/drm/i915/gt/intel_ring_submission.c

709

*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));

drivers/gpu/drm/i915/gt/intel_ring_submission.c

714

*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));

drivers/gpu/drm/i915/gt/intel_ring_submission.c

719

*cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));

drivers/gpu/drm/i915/gt/intel_ring_submission.c

768

RING_PSMI_CTL(signaller->mmio_base));

drivers/gpu/drm/i915/gt/intel_ring_submission.c

821

last_reg = RING_PSMI_CTL(signaller->mmio_base);

drivers/gpu/drm/i915/gt/intel_workarounds.c

1501

wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base),

drivers/gpu/drm/i915/gt/intel_workarounds.c

1620

wa_write_or(wal, VDBOX_CGCTL3F1C(engine->mmio_base),

drivers/gpu/drm/i915/gt/intel_workarounds.c

1998

RING_CTX_TIMESTAMP(engine->mmio_base),

drivers/gpu/drm/i915/gt/intel_workarounds.c

2042

whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),

drivers/gpu/drm/i915/gt/intel_workarounds.c

2045

whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),

drivers/gpu/drm/i915/gt/intel_workarounds.c

2048

whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),

drivers/gpu/drm/i915/gt/intel_workarounds.c

2169

const u32 base = engine->mmio_base;

drivers/gpu/drm/i915/gt/intel_workarounds.c

2226

RING_CMD_CCTL(engine->mmio_base),

drivers/gpu/drm/i915/gt/intel_workarounds.c

2693

RING_SEMA_WAIT_POLL(engine->mmio_base),

drivers/gpu/drm/i915/gt/intel_workarounds.c

2698

wa_masked_field_set(wal, ECOSKPD(engine->mmio_base),

drivers/gpu/drm/i915/gt/intel_workarounds.c

890

wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN);

drivers/gpu/drm/i915/gt/intel_workarounds.c

906

BLIT_CCTL(engine->mmio_base),

drivers/gpu/drm/i915/gt/selftest_engine_cs.c

49

return RING_TIMESTAMP_UDW(engine->mmio_base);

drivers/gpu/drm/i915/gt/selftest_engine_cs.c

51

return RING_TIMESTAMP(engine->mmio_base);

drivers/gpu/drm/i915/gt/selftest_engine_pm.c

102

cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4016);

drivers/gpu/drm/i915/gt/selftest_engine_pm.c

103

cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4012);

drivers/gpu/drm/i915/gt/selftest_engine_pm.c

96

cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4000);

drivers/gpu/drm/i915/gt/selftest_engine_pm.c

97

cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4004);

drivers/gpu/drm/i915/gt/selftest_execlists.c

1091

*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));

drivers/gpu/drm/i915/gt/selftest_execlists.c

27

#define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)

drivers/gpu/drm/i915/gt/selftest_lrc.c

27

#define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)

drivers/gpu/drm/i915/gt/selftest_lrc.c

305

i915_mmio_reg_offset(RING_START(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

310

i915_mmio_reg_offset(RING_CTL(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

315

i915_mmio_reg_offset(RING_HEAD(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

320

i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

325

i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

330

i915_mmio_reg_offset(RING_BBSTATE(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

335

i915_mmio_reg_offset(RING_BB_PER_CTX_PTR(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

340

i915_mmio_reg_offset(RING_INDIRECT_CTX(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

345

i915_mmio_reg_offset(RING_INDIRECT_CTX_OFFSET(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

350

i915_mmio_reg_offset(RING_CTX_TIMESTAMP(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

355

i915_mmio_reg_offset(GEN8_RING_CS_GPR(engine->mmio_base, 0)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

360

i915_mmio_reg_offset(RING_CMD_BUF_CCTL(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

365

i915_mmio_reg_offset(RING_BB_OFFSET(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

445

*cs++ = i915_mmio_reg_offset(RING_START(engine->mmio_base));

drivers/gpu/drm/i915/gt/selftest_lrc.c

452

*cs++ = i915_mmio_reg_offset(RING_TAIL(engine->mmio_base));

drivers/gpu/drm/i915/gt/selftest_lrc.c

769

*cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(rq->engine->mmio_base));

drivers/gpu/drm/i915/gt/selftest_rps.c

68

#define CS_GPR(x) GEN8_RING_CS_GPR(engine->mmio_base, x)

drivers/gpu/drm/i915/gt/selftest_timeline.c

778

const u32 gpr = i915_mmio_reg_offset(GEN8_RING_CS_GPR(rq->engine->mmio_base, 0));

drivers/gpu/drm/i915/gt/selftest_workarounds.c

102

const u32 base = engine->mmio_base;

drivers/gpu/drm/i915/gt/selftest_workarounds.c

182

RING_NOPID(engine->mmio_base);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

438

reg = (reg - engine->mmio_base) & ~RING_FORCE_TO_NONPRIV_ACCESS_MASK;

drivers/gpu/drm/i915/gt/sysfs_engines.c

55

return sysfs_emit(buf, "0x%x\n", kobj_to_engine(kobj)->mmio_base);

drivers/gpu/drm/i915/gt/sysfs_engines.c

59

__ATTR(mmio_base, 0444, mmio_show, NULL);

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c

379

const u32 base = engine->mmio_base;

drivers/gpu/drm/i915/gvt/cmd_parser.c

860

u32 base = s->workload->engine->mmio_base;

drivers/gpu/drm/i915/gvt/execlist.c

42

#define execlist_ring_mmio(e, offset) ((e)->mmio_base + (offset))

drivers/gpu/drm/i915/gvt/handlers.c

179

if (engine->mmio_base == offset)

drivers/gpu/drm/i915/gvt/handlers.c

1986

offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) ||

drivers/gpu/drm/i915/gvt/handlers.c

1987

offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(engine->mmio_base))) {

drivers/gpu/drm/i915/gvt/handlers.c

805

reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) {

drivers/gpu/drm/i915/gvt/scheduler.c

281

reg = RING_INSTDONE(engine->mmio_base);

drivers/gpu/drm/i915/gvt/scheduler.c

285

reg = RING_ACTHD(engine->mmio_base);

drivers/gpu/drm/i915/gvt/scheduler.c

289

reg = RING_ACTHD_UDW(engine->mmio_base);

drivers/gpu/drm/i915/gvt/scheduler.c

661

vgpu_vreg_t(workload->vgpu, RING_START(workload->engine->mmio_base)) =

drivers/gpu/drm/i915/gvt/scheduler.c

979

ring_base = rq->engine->mmio_base;

drivers/gpu/drm/i915/i915_gpu_error.c

1378

mmio = RING_HWS_PGA_GEN6(engine->mmio_base);

drivers/gpu/drm/i915/i915_gpu_error.c

1381

mmio = RING_HWS_PGA(engine->mmio_base);

drivers/gpu/drm/i915/i915_gpu_error.c

1401

u32 base = engine->mmio_base;

drivers/gpu/drm/i915/i915_perf.c

1384

err = __read_reg(ce, RING_EXECLIST_STATUS_HI(ce->engine->mmio_base),

drivers/gpu/drm/i915/i915_perf.c

1492

i915_reg_t reg = GEN12_OACTXCONTROL(ce->engine->mmio_base);

drivers/gpu/drm/i915/i915_perf.c

1945

const u32 base = stream->engine->mmio_base;

drivers/gpu/drm/i915/i915_perf.c

2636

RING_CONTEXT_CONTROL(ce->engine->mmio_base),

drivers/gpu/drm/i915/selftests/i915_perf.c

307

gpr0 = i915_mmio_reg_offset(GEN8_RING_CS_GPR(stream->engine->mmio_base, 0));

drivers/gpu/drm/i915/selftests/i915_request.c

1962

*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP((ce->engine->mmio_base)));

drivers/gpu/drm/i915/selftests/intel_uncore.c

211

i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset);

drivers/gpu/drm/i915/selftests/intel_uncore.c

212

u32 __iomem *reg = intel_uncore_regs(uncore) + engine->mmio_base + r->offset;

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

686

void __iomem *mmio_base, struct mdp5_cfg_handler *cfg_hnd)

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h

18

void __iomem *mmio_base, struct mdp5_cfg_handler *cfg_hnd);

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

3148

u64 mmio_base, mmio_size;

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

3169

mmio_base = device->func->resource_addr(device, NVKM_BAR0_PRI);

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

3172

device->pri = ioremap(mmio_base, mmio_size);

drivers/gpu/drm/xe/xe_execlist.c

175

lo = xe_mmio_read32(&gt->mmio, RING_EXECLIST_STATUS_LO(hwe->mmio_base));

drivers/gpu/drm/xe/xe_execlist.c

176

hi = xe_mmio_read32(&gt->mmio, RING_EXECLIST_STATUS_HI(hwe->mmio_base));

drivers/gpu/drm/xe/xe_execlist.c

81

xe_mmio_write32(mmio, RING_HWS_PGA(hwe->mmio_base),

drivers/gpu/drm/xe/xe_execlist.c

83

xe_mmio_read32(mmio, RING_HWS_PGA(hwe->mmio_base));

drivers/gpu/drm/xe/xe_execlist.c

87

xe_mmio_write32(mmio, RING_MODE(hwe->mmio_base), ring_mode);

drivers/gpu/drm/xe/xe_execlist.c

89

xe_mmio_write32(mmio, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base),

drivers/gpu/drm/xe/xe_execlist.c

91

xe_mmio_write32(mmio, RING_EXECLIST_SQ_CONTENTS_HI(hwe->mmio_base),

drivers/gpu/drm/xe/xe_execlist.c

93

xe_mmio_write32(mmio, RING_EXECLIST_CONTROL(hwe->mmio_base),

drivers/gpu/drm/xe/xe_gt.c

314

*cs++ = CS_MMIO_GROUP_INSTANCE_SELECT(hwe->mmio_base).addr;

drivers/gpu/drm/xe/xe_gt.c

363

*cs++ = CS_MMIO_GROUP_INSTANCE_SELECT(q->hwe->mmio_base).addr;

drivers/gpu/drm/xe/xe_guc_ads.c

745

{ .reg = RING_MODE(hwe->mmio_base), },

drivers/gpu/drm/xe/xe_guc_ads.c

746

{ .reg = RING_HWS_PGA(hwe->mmio_base), },

drivers/gpu/drm/xe/xe_guc_ads.c

747

{ .reg = RING_IMR(hwe->mmio_base), },

drivers/gpu/drm/xe/xe_hw_engine.c

103

.mmio_base = XEHPC_BCS4_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

1065

return xe_mmio_read64_2x32(&hwe->gt->mmio, RING_TIMESTAMP(hwe->mmio_base));

drivers/gpu/drm/xe/xe_hw_engine.c

111

.mmio_base = XEHPC_BCS5_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

119

.mmio_base = XEHPC_BCS6_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

127

.mmio_base = XEHPC_BCS7_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

135

.mmio_base = XEHPC_BCS8_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

144

.mmio_base = BSD_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

152

.mmio_base = BSD2_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

160

.mmio_base = BSD3_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

168

.mmio_base = BSD4_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

176

.mmio_base = XEHP_BSD5_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

184

.mmio_base = XEHP_BSD6_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

192

.mmio_base = XEHP_BSD7_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

200

.mmio_base = XEHP_BSD8_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

208

.mmio_base = VEBOX_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

216

.mmio_base = VEBOX2_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

224

.mmio_base = XEHP_VEBOX3_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

232

.mmio_base = XEHP_VEBOX4_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

240

.mmio_base = COMPUTE0_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

248

.mmio_base = COMPUTE1_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

256

.mmio_base = COMPUTE2_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

264

.mmio_base = COMPUTE3_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

271

.mmio_base = GSCCS_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

298

xe_gt_assert(hwe->gt, !(reg.addr & hwe->mmio_base));

drivers/gpu/drm/xe/xe_hw_engine.c

301

reg.addr += hwe->mmio_base;

drivers/gpu/drm/xe/xe_hw_engine.c

318

xe_gt_assert(hwe->gt, !(reg.addr & hwe->mmio_base));

drivers/gpu/drm/xe/xe_hw_engine.c

321

reg.addr += hwe->mmio_base;

drivers/gpu/drm/xe/xe_hw_engine.c

520

hwe->mmio_base = info->mmio_base;

drivers/gpu/drm/xe/xe_hw_engine.c

53

u32 mmio_base;

drivers/gpu/drm/xe/xe_hw_engine.c

588

idledly = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base));

drivers/gpu/drm/xe/xe_hw_engine.c

589

maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));

drivers/gpu/drm/xe/xe_hw_engine.c

601

xe_mmio_write32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base), idledly);

drivers/gpu/drm/xe/xe_hw_engine.c

63

.mmio_base = RENDER_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

71

.mmio_base = BLT_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

79

.mmio_base = XEHPC_BCS1_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

87

.mmio_base = XEHPC_BCS2_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine.c

941

snapshot->mmio_base = hwe->mmio_base;

drivers/gpu/drm/xe/xe_hw_engine.c

95

.mmio_base = XEHPC_BCS3_RING_BASE,

drivers/gpu/drm/xe/xe_hw_engine_types.h

122

u32 mmio_base;

drivers/gpu/drm/xe/xe_hw_engine_types.h

180

u32 mmio_base;

drivers/gpu/drm/xe/xe_lrc.c

187

const u32 base = hwe->mmio_base;

drivers/gpu/drm/xe/xe_lrc.c

2401

RING_CTX_TIMESTAMP(hwe->mmio_base));

drivers/gpu/drm/xe/xe_lrc.c

2404

RING_CTX_TIMESTAMP(hwe->mmio_base));

drivers/gpu/drm/xe/xe_oa.c

751

OACTXCONTROL(stream->hwe->mmio_base),

drivers/gpu/drm/xe/xe_oa.c

759

RING_CONTEXT_CONTROL(stream->hwe->mmio_base),

drivers/gpu/drm/xe/xe_oa.c

775

OACTXCONTROL(stream->hwe->mmio_base),

drivers/gpu/drm/xe/xe_oa.c

783

RING_CONTEXT_CONTROL(stream->hwe->mmio_base),

drivers/gpu/drm/xe/xe_query.c

98

struct xe_reg upper_reg = RING_TIMESTAMP_UDW(hwe->mmio_base),

drivers/gpu/drm/xe/xe_query.c

99

lower_reg = RING_TIMESTAMP(hwe->mmio_base);

drivers/gpu/drm/xe/xe_reg_whitelist.c

151

.reg = RING_FORCE_TO_NONPRIV(hwe->mmio_base, slot),

drivers/gpu/drm/xe/xe_rtp.c

169

u32 mmio_base,

drivers/gpu/drm/xe/xe_rtp.c

179

sr_entry.reg.addr += mmio_base;

drivers/gpu/drm/xe/xe_rtp.c

188

u32 mmio_base;

drivers/gpu/drm/xe/xe_rtp.c

197

mmio_base = hwe->mmio_base;

drivers/gpu/drm/xe/xe_rtp.c

199

mmio_base = 0;

drivers/gpu/drm/xe/xe_rtp.c

201

rtp_add_sr_entry(action, gt, mmio_base, sr);

drivers/input/keyboard/ep93xx_keypad.c

138

__raw_writel(val, keypad->mmio_base + KEY_INIT);

drivers/input/keyboard/ep93xx_keypad.c

218

keypad->mmio_base = devm_platform_ioremap_resource(pdev, 0);

drivers/input/keyboard/ep93xx_keypad.c

219

if (IS_ERR(keypad->mmio_base))

drivers/input/keyboard/ep93xx_keypad.c

220

return PTR_ERR(keypad->mmio_base);

drivers/input/keyboard/ep93xx_keypad.c

67

void __iomem *mmio_base;

drivers/input/keyboard/ep93xx_keypad.c

86

status = __raw_readl(keypad->mmio_base + KEY_REG);

drivers/input/keyboard/imx_keypad.c

100

writew(reg_val, keypad->mmio_base + KPCR);

drivers/input/keyboard/imx_keypad.c

104

reg_val = readw(keypad->mmio_base + KPCR);

drivers/input/keyboard/imx_keypad.c

106

writew(reg_val, keypad->mmio_base + KPCR);

drivers/input/keyboard/imx_keypad.c

113

reg_val = readw(keypad->mmio_base + KPDR);

drivers/input/keyboard/imx_keypad.c

115

writew(reg_val, keypad->mmio_base + KPDR);

drivers/input/keyboard/imx_keypad.c

127

reg_val = readw(keypad->mmio_base + KPDR);

drivers/input/keyboard/imx_keypad.c

135

reg_val = readw(keypad->mmio_base + KPDR);

drivers/input/keyboard/imx_keypad.c

137

writew(reg_val, keypad->mmio_base + KPDR);

drivers/input/keyboard/imx_keypad.c

260

reg_val = readw(keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

262

writew(reg_val, keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

264

reg_val = readw(keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

267

writew(reg_val, keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

278

reg_val = readw(keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

280

writew(reg_val, keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

282

reg_val = readw(keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

285

writew(reg_val, keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

294

reg_val = readw(keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

300

writew(reg_val, keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

322

reg_val = readw(keypad->mmio_base + KPCR);

drivers/input/keyboard/imx_keypad.c

325

writew(reg_val, keypad->mmio_base + KPCR);

drivers/input/keyboard/imx_keypad.c

328

reg_val = readw(keypad->mmio_base + KPDR);

drivers/input/keyboard/imx_keypad.c

330

writew(reg_val, keypad->mmio_base + KPDR);

drivers/input/keyboard/imx_keypad.c

333

writew(0xff00, keypad->mmio_base + KDDR);

drivers/input/keyboard/imx_keypad.c

339

reg_val = readw(keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

342

writew(reg_val, keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

347

writew(reg_val, keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

355

reg_val = readw(keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

358

writew(reg_val, keypad->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

362

writew(reg_val, keypad->mmio_base + KPCR);

drivers/input/keyboard/imx_keypad.c

400

if ((readw(keypad->mmio_base + KPDR) & keypad->rows_en_mask) == 0) {

drivers/input/keyboard/imx_keypad.c

448

keypad->mmio_base = devm_platform_ioremap_resource(pdev, 0);

drivers/input/keyboard/imx_keypad.c

449

if (IS_ERR(keypad->mmio_base))

drivers/input/keyboard/imx_keypad.c

450

return PTR_ERR(keypad->mmio_base);

drivers/input/keyboard/imx_keypad.c

49

void __iomem *mmio_base;

drivers/input/keyboard/imx_keypad.c

523

unsigned short reg_val = readw(kbd->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

536

writew(reg_val, kbd->mmio_base + KPSR);

drivers/input/keyboard/imx_keypad.c

94

reg_val = readw(keypad->mmio_base + KPDR);

drivers/input/keyboard/imx_keypad.c

96

writew(reg_val, keypad->mmio_base + KPDR);

drivers/input/keyboard/imx_keypad.c

98

reg_val = readw(keypad->mmio_base + KPCR);

drivers/input/keyboard/pxa27x_keypad.c

100

#define keypad_readl(off) __raw_readl(keypad->mmio_base + (off))

drivers/input/keyboard/pxa27x_keypad.c

101

#define keypad_writel(off, v) __raw_writel((v), keypad->mmio_base + (off))

drivers/input/keyboard/pxa27x_keypad.c

120

void __iomem *mmio_base;

drivers/input/keyboard/pxa27x_keypad.c

634

keypad->mmio_base = devm_platform_ioremap_resource(pdev, 0);

drivers/input/keyboard/pxa27x_keypad.c

635

if (IS_ERR(keypad->mmio_base))

drivers/input/keyboard/pxa27x_keypad.c

636

return PTR_ERR(keypad->mmio_base);

drivers/iommu/amd/amd_iommu_types.h

656

u8 __iomem *mmio_base;

drivers/iommu/amd/debugfs.c

123

head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);

drivers/iommu/amd/debugfs.c

124

tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);

drivers/iommu/amd/debugfs.c

58

value = readq(iommu->mmio_base + iommu->dbg_mmio_offset);

drivers/iommu/amd/init.c

1000

paddr = readq(iommu->mmio_base + MMIO_CMD_BUF_OFFSET) & PM_ADDR_MASK;

drivers/iommu/amd/init.c

1016

paddr = readq(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET) & PM_ADDR_MASK;

drivers/iommu/amd/init.c

1152

lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET);

drivers/iommu/amd/init.c

1153

hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4);

drivers/iommu/amd/init.c

1945

iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,

drivers/iommu/amd/init.c

1947

if (!iommu->mmio_base)

drivers/iommu/amd/init.c

2079

val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);

drivers/iommu/amd/init.c

2132

features = readq(iommu->mmio_base + MMIO_EXT_FEATURES);

drivers/iommu/amd/init.c

2133

features2 = readq(iommu->mmio_base + MMIO_EXT_FEATURES2);

drivers/iommu/amd/init.c

2446

writeq(xt.capxt, iommu->mmio_base + irqd->hwirq);

drivers/iommu/amd/init.c

2453

writeq(0, iommu->mmio_base + irqd->hwirq);

drivers/iommu/amd/init.c

246

ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);

drivers/iommu/amd/init.c

2867

ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);

drivers/iommu/amd/init.c

2990

status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);

drivers/iommu/amd/init.c

3002

status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);

drivers/iommu/amd/init.c

369

memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,

drivers/iommu/amd/init.c

373

memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,

drivers/iommu/amd/init.c

389

memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,

drivers/iommu/amd/init.c

3944

writel((u32)val, iommu->mmio_base + offset);

drivers/iommu/amd/init.c

3945

writel((val >> 32), iommu->mmio_base + offset + 4);

drivers/iommu/amd/init.c

3947

*value = readl(iommu->mmio_base + offset + 4);

drivers/iommu/amd/init.c

3949

*value |= readl(iommu->mmio_base + offset);

drivers/iommu/amd/init.c

396

memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,

drivers/iommu/amd/init.c

407

BUG_ON(iommu->mmio_base == NULL);

drivers/iommu/amd/init.c

414

memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,

drivers/iommu/amd/init.c

422

ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);

drivers/iommu/amd/init.c

426

writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);

drivers/iommu/amd/init.c

448

if (!iommu->mmio_base)

drivers/iommu/amd/init.c

491

if (iommu->mmio_base)

drivers/iommu/amd/init.c

492

iounmap(iommu->mmio_base);

drivers/iommu/amd/init.c

758

status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);

drivers/iommu/amd/init.c

767

writel(status_overflow_mask, iommu->mmio_base + MMIO_STATUS_OFFSET);

drivers/iommu/amd/init.c

803

writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);

drivers/iommu/amd/init.c

804

writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);

drivers/iommu/amd/init.c

828

memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,

drivers/iommu/amd/init.c

887

memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,

drivers/iommu/amd/init.c

892

writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);

drivers/iommu/amd/init.c

893

writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);

drivers/iommu/amd/init.c

929

memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET,

drivers/iommu/amd/init.c

933

memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET,

drivers/iommu/amd/init.c

935

writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);

drivers/iommu/amd/init.c

936

writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET);

drivers/iommu/amd/init.c

943

status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);

drivers/iommu/amd/init.c

989

paddr = readq(iommu->mmio_base + MMIO_EVT_BUF_OFFSET) & PM_ADDR_MASK;

drivers/iommu/amd/iommu.c

1005

head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);

drivers/iommu/amd/iommu.c

1006

tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);

drivers/iommu/amd/iommu.c

1013

writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);

drivers/iommu/amd/iommu.c

1044

head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);

drivers/iommu/amd/iommu.c

1045

tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);

drivers/iommu/amd/iommu.c

1058

writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);

drivers/iommu/amd/iommu.c

1100

u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);

drivers/iommu/amd/iommu.c

1105

writel(mask, iommu->mmio_base + MMIO_STATUS_OFFSET);

drivers/iommu/amd/iommu.c

1129

status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);

drivers/iommu/amd/iommu.c

1183

head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);

drivers/iommu/amd/iommu.c

1184

tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);

drivers/iommu/amd/iommu.c

1240

writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);

drivers/iommu/amd/iommu.c

1404

iommu->cmd_buf_head = readl(iommu->mmio_base +

drivers/iommu/amd/iommu.c

919

ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);

drivers/iommu/amd/ppr.c

169

head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);

drivers/iommu/amd/ppr.c

170

tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);

drivers/iommu/amd/ppr.c

205

writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);

drivers/iommu/amd/ppr.c

38

memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,

drivers/iommu/amd/ppr.c

42

writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);

drivers/iommu/amd/ppr.c

43

writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);

drivers/media/platform/ti/omap3isp/isp.c

2293

isp->mmio_base[map_idx] =

drivers/media/platform/ti/omap3isp/isp.c

2295

if (IS_ERR(isp->mmio_base[map_idx])) {

drivers/media/platform/ti/omap3isp/isp.c

2296

ret = PTR_ERR(isp->mmio_base[map_idx]);

drivers/media/platform/ti/omap3isp/isp.c

2341

isp->mmio_base[i] =

drivers/media/platform/ti/omap3isp/isp.c

2342

isp->mmio_base[0] + isp_res_maps[m].offset[i];

drivers/media/platform/ti/omap3isp/isp.c

2345

isp->mmio_base[i] =

drivers/media/platform/ti/omap3isp/isp.c

2346

isp->mmio_base[OMAP3_ISP_IOMEM_CSI2A_REGS1]

drivers/media/platform/ti/omap3isp/isp.h

182

void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST];

drivers/media/platform/ti/omap3isp/isp.h

287

return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset);

drivers/media/platform/ti/omap3isp/isp.h

301

__raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);

drivers/misc/vmw_vmci/vmci_guest.c

104

if (dev->mmio_base != NULL)

drivers/misc/vmw_vmci/vmci_guest.c

105

return readl(dev->mmio_base + reg);

drivers/misc/vmw_vmci/vmci_guest.c

111

if (dev->mmio_base != NULL)

drivers/misc/vmw_vmci/vmci_guest.c

112

writel(val, dev->mmio_base + reg);

drivers/misc/vmw_vmci/vmci_guest.c

120

if (vmci_dev->mmio_base == NULL)

drivers/misc/vmw_vmci/vmci_guest.c

152

if (dev->mmio_base != NULL) {

drivers/misc/vmw_vmci/vmci_guest.c

312

bool is_io_port = vmci_dev->mmio_base == NULL;

drivers/misc/vmw_vmci/vmci_guest.c

55

void __iomem *mmio_base;

drivers/misc/vmw_vmci/vmci_guest.c

555

if (vmci_dev->mmio_base != NULL) {

drivers/misc/vmw_vmci/vmci_guest.c

579

void __iomem *mmio_base = NULL;

drivers/misc/vmw_vmci/vmci_guest.c

604

mmio_base = pci_iomap_range(pdev, 1, VMCI_MMIO_ACCESS_OFFSET,

drivers/misc/vmw_vmci/vmci_guest.c

607

if (!mmio_base)

drivers/misc/vmw_vmci/vmci_guest.c

611

if (!mmio_base) {

drivers/misc/vmw_vmci/vmci_guest.c

635

vmci_dev->mmio_base = mmio_base;

drivers/misc/vmw_vmci/vmci_guest.c

639

if (mmio_base != NULL) {

drivers/misc/vmw_vmci/vmci_guest.c

713

if (mmio_base != NULL) {

drivers/misc/vmw_vmci/vmci_guest.c

785

if (vmci_dev->mmio_base != NULL)

drivers/misc/vmw_vmci/vmci_guest.c

898

if (mmio_base != NULL)

drivers/misc/vmw_vmci/vmci_guest.c

899

pci_iounmap(pdev, mmio_base);

drivers/misc/vmw_vmci/vmci_guest.c

937

if (vmci_dev->mmio_base != NULL)

drivers/misc/vmw_vmci/vmci_guest.c

956

if (vmci_dev->mmio_base != NULL)

drivers/misc/vmw_vmci/vmci_guest.c

957

pci_iounmap(pdev, vmci_dev->mmio_base);

drivers/net/ethernet/broadcom/bgmac.c

107

bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);

drivers/net/ethernet/broadcom/bgmac.c

200

bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,

drivers/net/ethernet/broadcom/bgmac.c

225

ring->mmio_base);

drivers/net/ethernet/broadcom/bgmac.c

242

empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);

drivers/net/ethernet/broadcom/bgmac.c

294

if (!ring->mmio_base)

drivers/net/ethernet/broadcom/bgmac.c

297

bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);

drivers/net/ethernet/broadcom/bgmac.c

299

ring->mmio_base + BGMAC_DMA_RX_STATUS,

drivers/net/ethernet/broadcom/bgmac.c

303

ring->mmio_base);

drivers/net/ethernet/broadcom/bgmac.c

311

ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);

drivers/net/ethernet/broadcom/bgmac.c

330

bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);

drivers/net/ethernet/broadcom/bgmac.c

372

bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,

drivers/net/ethernet/broadcom/bgmac.c

418

end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);

drivers/net/ethernet/broadcom/bgmac.c

46

if (!ring->mmio_base)

drivers/net/ethernet/broadcom/bgmac.c

510

bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,

drivers/net/ethernet/broadcom/bgmac.c

512

if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))

drivers/net/ethernet/broadcom/bgmac.c

516

bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,

drivers/net/ethernet/broadcom/bgmac.c

518

if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))

drivers/net/ethernet/broadcom/bgmac.c

53

bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,

drivers/net/ethernet/broadcom/bgmac.c

56

val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);

drivers/net/ethernet/broadcom/bgmac.c

633

ring->mmio_base = ring_base[i];

drivers/net/ethernet/broadcom/bgmac.c

642

ring->mmio_base);

drivers/net/ethernet/broadcom/bgmac.c

658

ring->mmio_base = ring_base[i];

drivers/net/ethernet/broadcom/bgmac.c

667

ring->mmio_base);

drivers/net/ethernet/broadcom/bgmac.c

68

ring->mmio_base, val);

drivers/net/ethernet/broadcom/bgmac.c

696

bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,

drivers/net/ethernet/broadcom/bgmac.c

698

bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,

drivers/net/ethernet/broadcom/bgmac.c

71

bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);

drivers/net/ethernet/broadcom/bgmac.c

714

bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,

drivers/net/ethernet/broadcom/bgmac.c

716

bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,

drivers/net/ethernet/broadcom/bgmac.c

73

ring->mmio_base + BGMAC_DMA_TX_STATUS,

drivers/net/ethernet/broadcom/bgmac.c

77

ring->mmio_base);

drivers/net/ethernet/broadcom/bgmac.c

79

val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);

drivers/net/ethernet/broadcom/bgmac.c

82

ring->mmio_base);

drivers/net/ethernet/broadcom/bgmac.c

91

ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);

drivers/net/ethernet/broadcom/bgmac.h

427

u16 mmio_base;

drivers/net/wireless/broadcom/b43/dma.c

1739

u16 mmio_base, bool enable)

drivers/net/wireless/broadcom/b43/dma.c

1744

ctl = b43_read32(dev, mmio_base + B43_DMA64_RXCTL);

drivers/net/wireless/broadcom/b43/dma.c

1748

b43_write32(dev, mmio_base + B43_DMA64_RXCTL, ctl);

drivers/net/wireless/broadcom/b43/dma.c

1750

ctl = b43_read32(dev, mmio_base + B43_DMA32_RXCTL);

drivers/net/wireless/broadcom/b43/dma.c

1754

b43_write32(dev, mmio_base + B43_DMA32_RXCTL, ctl);

drivers/net/wireless/broadcom/b43/dma.c

1764

u16 mmio_base;

drivers/net/wireless/broadcom/b43/dma.c

1768

mmio_base = b43_dmacontroller_base(type, engine_index);

drivers/net/wireless/broadcom/b43/dma.c

1769

direct_fifo_rx(dev, type, mmio_base, enable);

drivers/net/wireless/broadcom/b43/dma.c

439

static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base,

drivers/net/wireless/broadcom/b43/dma.c

449

b43_write32(dev, mmio_base + offset, 0);

drivers/net/wireless/broadcom/b43/dma.c

453

value = b43_read32(dev, mmio_base + offset);

drivers/net/wireless/broadcom/b43/dma.c

478

static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base,

drivers/net/wireless/broadcom/b43/dma.c

490

value = b43_read32(dev, mmio_base + offset);

drivers/net/wireless/broadcom/b43/dma.c

507

b43_write32(dev, mmio_base + offset, 0);

drivers/net/wireless/broadcom/b43/dma.c

511

value = b43_read32(dev, mmio_base + offset);

drivers/net/wireless/broadcom/b43/dma.c

756

b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,

drivers/net/wireless/broadcom/b43/dma.c

764

b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,

drivers/net/wireless/broadcom/b43/dma.c

803

u16 mmio_base;

drivers/net/wireless/broadcom/b43/dma.c

822

mmio_base = b43_dmacontroller_base(0, 0);

drivers/net/wireless/broadcom/b43/dma.c

823

b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);

drivers/net/wireless/broadcom/b43/dma.c

824

tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);

drivers/net/wireless/broadcom/b43/dma.c

857

ring->mmio_base = b43_dmacontroller_base(type, controller_index);

drivers/net/wireless/broadcom/b43/dma.h

251

u16 mmio_base;

drivers/net/wireless/broadcom/b43/dma.h

280

return b43_read32(ring->dev, ring->mmio_base + offset);

drivers/net/wireless/broadcom/b43/dma.h

285

b43_write32(ring->dev, ring->mmio_base + offset, value);

drivers/net/wireless/broadcom/b43/pio.c

135

q->mmio_base = index_to_pioqueue_base(dev, index) +

drivers/net/wireless/broadcom/b43/pio.c

169

q->mmio_base = index_to_pioqueue_base(dev, index) +

drivers/net/wireless/broadcom/b43/pio.c

330

q->mmio_base + B43_PIO_TXDATA,

drivers/net/wireless/broadcom/b43/pio.c

342

q->mmio_base + B43_PIO_TXDATA,

drivers/net/wireless/broadcom/b43/pio.c

384

q->mmio_base + B43_PIO8_TXDATA,

drivers/net/wireless/broadcom/b43/pio.c

412

q->mmio_base + B43_PIO8_TXDATA,

drivers/net/wireless/broadcom/b43/pio.c

658

q->mmio_base + B43_PIO8_RXDATA,

drivers/net/wireless/broadcom/b43/pio.c

662

q->mmio_base + B43_PIO_RXDATA,

drivers/net/wireless/broadcom/b43/pio.c

706

q->mmio_base + B43_PIO8_RXDATA,

drivers/net/wireless/broadcom/b43/pio.c

714

q->mmio_base + B43_PIO8_RXDATA,

drivers/net/wireless/broadcom/b43/pio.c

733

q->mmio_base + B43_PIO_RXDATA,

drivers/net/wireless/broadcom/b43/pio.c

741

q->mmio_base + B43_PIO_RXDATA,

drivers/net/wireless/broadcom/b43/pio.h

101

u16 mmio_base;

drivers/net/wireless/broadcom/b43/pio.h

111

return b43_read16(q->dev, q->mmio_base + offset);

drivers/net/wireless/broadcom/b43/pio.h

116

return b43_read32(q->dev, q->mmio_base + offset);

drivers/net/wireless/broadcom/b43/pio.h

122

b43_write16(q->dev, q->mmio_base + offset, value);

drivers/net/wireless/broadcom/b43/pio.h

128

b43_write32(q->dev, q->mmio_base + offset, value);

drivers/net/wireless/broadcom/b43/pio.h

134

return b43_read16(q->dev, q->mmio_base + offset);

drivers/net/wireless/broadcom/b43/pio.h

139

return b43_read32(q->dev, q->mmio_base + offset);

drivers/net/wireless/broadcom/b43/pio.h

145

b43_write16(q->dev, q->mmio_base + offset, value);

drivers/net/wireless/broadcom/b43/pio.h

151

b43_write32(q->dev, q->mmio_base + offset, value);

drivers/net/wireless/broadcom/b43/pio.h

72

u16 mmio_base;

drivers/net/wireless/broadcom/b43legacy/dma.c

317

u16 mmio_base,

drivers/net/wireless/broadcom/b43legacy/dma.c

327

b43legacy_write32(dev, mmio_base + offset, 0);

drivers/net/wireless/broadcom/b43legacy/dma.c

330

value = b43legacy_read32(dev, mmio_base + offset);

drivers/net/wireless/broadcom/b43legacy/dma.c

348

u16 mmio_base,

drivers/net/wireless/broadcom/b43legacy/dma.c

359

value = b43legacy_read32(dev, mmio_base + offset);

drivers/net/wireless/broadcom/b43legacy/dma.c

368

b43legacy_write32(dev, mmio_base + offset, 0);

drivers/net/wireless/broadcom/b43legacy/dma.c

371

value = b43legacy_read32(dev, mmio_base + offset);

drivers/net/wireless/broadcom/b43legacy/dma.c

551

b43legacy_dmacontroller_tx_reset(ring->dev, ring->mmio_base,

drivers/net/wireless/broadcom/b43legacy/dma.c

555

b43legacy_dmacontroller_rx_reset(ring->dev, ring->mmio_base,

drivers/net/wireless/broadcom/b43legacy/dma.c

588

u16 mmio_base;

drivers/net/wireless/broadcom/b43legacy/dma.c

590

mmio_base = b43legacy_dmacontroller_base(0, 0);

drivers/net/wireless/broadcom/b43legacy/dma.c

592

mmio_base + B43legacy_DMA32_TXCTL,

drivers/net/wireless/broadcom/b43legacy/dma.c

594

tmp = b43legacy_read32(dev, mmio_base +

drivers/net/wireless/broadcom/b43legacy/dma.c

664

ring->mmio_base = b43legacy_dmacontroller_base(type, controller_index);

drivers/net/wireless/broadcom/b43legacy/dma.c

712

" %d/%d\n", (unsigned int)(ring->type), ring->mmio_base,

drivers/net/wireless/broadcom/b43legacy/dma.h

145

u16 mmio_base;

drivers/net/wireless/broadcom/b43legacy/dma.h

171

return b43legacy_read32(ring->dev, ring->mmio_base + offset);

drivers/net/wireless/broadcom/b43legacy/dma.h

178

b43legacy_write32(ring->dev, ring->mmio_base + offset, value);

drivers/net/wireless/broadcom/b43legacy/pio.c

113

switch (queue->mmio_base) {

drivers/net/wireless/broadcom/b43legacy/pio.c

328

queue->mmio_base = pio_mmio_base;

drivers/net/wireless/broadcom/b43legacy/pio.c

340

qsize = b43legacy_read16(dev, queue->mmio_base

drivers/net/wireless/broadcom/b43legacy/pio.c

545

B43legacy_WARN_ON(queue->mmio_base != B43legacy_MMIO_PIO1_BASE);

drivers/net/wireless/broadcom/b43legacy/pio.c

585

if (unlikely(len == 0 && queue->mmio_base !=

drivers/net/wireless/broadcom/b43legacy/pio.c

591

if (queue->mmio_base == B43legacy_MMIO_PIO4_BASE)

drivers/net/wireless/broadcom/b43legacy/pio.c

603

(queue->mmio_base == B43legacy_MMIO_PIO1_BASE),

drivers/net/wireless/broadcom/b43legacy/pio.c

607

if (queue->mmio_base == B43legacy_MMIO_PIO4_BASE) {

drivers/net/wireless/broadcom/b43legacy/pio.h

53

u16 mmio_base;

drivers/net/wireless/broadcom/b43legacy/pio.h

87

return b43legacy_read16(queue->dev, queue->mmio_base + offset);

drivers/net/wireless/broadcom/b43legacy/pio.h

94

b43legacy_write16(queue->dev, queue->mmio_base + offset, value);

drivers/pci/controller/pci-hyperv.c

343

u64 mmio_base;

drivers/pci/controller/pci-hyperv.c

3472

d0_entry->mmio_base = hbus->mem_config->start;

drivers/pci/hotplug/shpchp.h

85

unsigned long mmio_base;

drivers/pci/hotplug/shpchp_hpc.c

574

release_mem_region(ctrl->mmio_base, ctrl->mmio_size);

drivers/pci/hotplug/shpchp_hpc.c

887

ctrl->mmio_base = pci_resource_start(pdev, 0);

drivers/pci/hotplug/shpchp_hpc.c

921

ctrl->mmio_base =

drivers/pci/hotplug/shpchp_hpc.c

936

if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {

drivers/pci/hotplug/shpchp_hpc.c

942

ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);

drivers/pci/hotplug/shpchp_hpc.c

945

ctrl->mmio_size, ctrl->mmio_base);

drivers/pci/hotplug/shpchp_hpc.c

946

release_mem_region(ctrl->mmio_base, ctrl->mmio_size);

drivers/pci/quirks.c

3973

void __iomem *mmio_base;

drivers/pci/quirks.c

3980

mmio_base = pci_iomap(dev, 0, 0);

drivers/pci/quirks.c

3981

if (!mmio_base)

drivers/pci/quirks.c

3984

iowrite32(0x00000002, mmio_base + MSG_CTL);

drivers/pci/quirks.c

3992

iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);

drivers/pci/quirks.c

3994

val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;

drivers/pci/quirks.c

3995

iowrite32(val, mmio_base + PCH_PP_CONTROL);

drivers/pci/quirks.c

3999

val = ioread32(mmio_base + PCH_PP_STATUS);

drivers/pci/quirks.c

4007

iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);

drivers/pci/quirks.c

4009

pci_iounmap(dev, mmio_base);

drivers/platform/mellanox/mlxbf-pmc.c

124

void __iomem *mmio_base;

drivers/platform/mellanox/mlxbf-pmc.c

1255

return mlxbf_pmc_write(pmc->block[blk_num].mmio_base +

drivers/platform/mellanox/mlxbf-pmc.c

1274

pmcaddr = pmc->block[blk_num].mmio_base +

drivers/platform/mellanox/mlxbf-pmc.c

1279

pmcaddr = pmc->block[blk_num].mmio_base +

drivers/platform/mellanox/mlxbf-pmc.c

1331

addr = pmc->block[blk_num].mmio_base +

drivers/platform/mellanox/mlxbf-pmc.c

1353

addr = pmc->block[blk_num].mmio_base +

drivers/platform/mellanox/mlxbf-pmc.c

1390

if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base +

drivers/platform/mellanox/mlxbf-pmc.c

1404

if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base +

drivers/platform/mellanox/mlxbf-pmc.c

1415

if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base +

drivers/platform/mellanox/mlxbf-pmc.c

1430

status = mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +

drivers/platform/mellanox/mlxbf-pmc.c

1438

status = mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +

drivers/platform/mellanox/mlxbf-pmc.c

1460

status = mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +

drivers/platform/mellanox/mlxbf-pmc.c

1497

status = mlxbf_pmc_write(pmc->block[blk_num].mmio_base + perfcfg_offset,

drivers/platform/mellanox/mlxbf-pmc.c

1504

return mlxbf_pmc_read(pmc->block[blk_num].mmio_base + perfval_offset,

drivers/platform/mellanox/mlxbf-pmc.c

1518

pmcaddr = pmc->block[blk_num].mmio_base +

drivers/platform/mellanox/mlxbf-pmc.c

1523

pmcaddr = pmc->block[blk_num].mmio_base +

drivers/platform/mellanox/mlxbf-pmc.c

1567

addr = pmc->block[blk_num].mmio_base +

drivers/platform/mellanox/mlxbf-pmc.c

1608

if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base + perfcfg_offset,

drivers/platform/mellanox/mlxbf-pmc.c

1613

if (mlxbf_pmc_read(pmc->block[blk_num].mmio_base + perfval_offset,

drivers/platform/mellanox/mlxbf-pmc.c

1629

if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + offset,

drivers/platform/mellanox/mlxbf-pmc.c

1638

return mlxbf_pmc_read(pmc->block[blk_num].mmio_base + offset,

drivers/platform/mellanox/mlxbf-pmc.c

1651

return mlxbf_pmc_write(pmc->block[blk_num].mmio_base + offset,

drivers/platform/mellanox/mlxbf-pmc.c

1656

return mlxbf_pmc_write(pmc->block[blk_num].mmio_base + offset,

drivers/platform/mellanox/mlxbf-pmc.c

1868

if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +

drivers/platform/mellanox/mlxbf-pmc.c

1875

if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +

drivers/platform/mellanox/mlxbf-pmc.c

1905

err = mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +

drivers/platform/mellanox/mlxbf-pmc.c

1916

mlxbf_pmc_write(pmc->block[blk_num].mmio_base +

drivers/platform/mellanox/mlxbf-pmc.c

1945

if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base +

drivers/platform/mellanox/mlxbf-pmc.c

1970

mlxbf_pmc_write(pmc->block[blk_num].mmio_base +

drivers/platform/mellanox/mlxbf-pmc.c

2239

pmc->block[i].mmio_base = (void __iomem *)info[0];

drivers/platform/mellanox/mlxbf-pmc.c

2241

pmc->block[i].mmio_base =

drivers/platform/mellanox/mlxbf-pmc.c

2248

if (!pmc->block[i].mmio_base)

drivers/platform/x86/intel/speed_select_if/isst_if_mmio.c

109

ret = pci_read_config_dword(pdev, 0xD0, &mmio_base);

drivers/platform/x86/intel/speed_select_if/isst_if_mmio.c

118

base_addr = (u64)mmio_base << 23 | (u64) pcu_base << 12;

drivers/platform/x86/intel/speed_select_if/isst_if_mmio.c

96

u32 mmio_base, pcu_base;

drivers/pwm/pwm-imx1.c

105

value = readl(imx->mmio_base + MX1_PWMC);

drivers/pwm/pwm-imx1.c

107

writel(value, imx->mmio_base + MX1_PWMC);

drivers/pwm/pwm-imx1.c

117

value = readl(imx->mmio_base + MX1_PWMC);

drivers/pwm/pwm-imx1.c

119

writel(value, imx->mmio_base + MX1_PWMC);

drivers/pwm/pwm-imx1.c

181

imx->mmio_base = devm_platform_ioremap_resource(pdev, 0);

drivers/pwm/pwm-imx1.c

182

if (IS_ERR(imx->mmio_base))

drivers/pwm/pwm-imx1.c

183

return PTR_ERR(imx->mmio_base);

drivers/pwm/pwm-imx1.c

30

void __iomem *mmio_base;

drivers/pwm/pwm-imx1.c

87

max = readl(imx->mmio_base + MX1_PWMP);

drivers/pwm/pwm-imx1.c

90

writel(max - p, imx->mmio_base + MX1_PWMS);

drivers/pwm/pwm-imx27.c

116

val = readl(imx->mmio_base + MX3_PWMCR);

drivers/pwm/pwm-imx27.c

136

val = readl(imx->mmio_base + MX3_PWMPR);

drivers/pwm/pwm-imx27.c

148

val = readl(imx->mmio_base + MX3_PWMSAR);

drivers/pwm/pwm-imx27.c

167

writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);

drivers/pwm/pwm-imx27.c

170

cr = readl(imx->mmio_base + MX3_PWMCR);

drivers/pwm/pwm-imx27.c

187

sr = readl(imx->mmio_base + MX3_PWMSR);

drivers/pwm/pwm-imx27.c

194

sr = readl(imx->mmio_base + MX3_PWMSR);

drivers/pwm/pwm-imx27.c

249

val = readl(imx->mmio_base + MX3_PWMPR);

drivers/pwm/pwm-imx27.c

251

cr = readl(imx->mmio_base + MX3_PWMCR);

drivers/pwm/pwm-imx27.c

319

val = FIELD_GET(MX3_PWMSR_FIFOAV, readl_relaxed(imx->mmio_base + MX3_PWMSR));

drivers/pwm/pwm-imx27.c

325

writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR);

drivers/pwm/pwm-imx27.c

326

writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR);

drivers/pwm/pwm-imx27.c

328

val = readl_relaxed(imx->mmio_base + MX3_PWMCNR);

drivers/pwm/pwm-imx27.c

335

writel_relaxed(imx->duty_cycle, imx->mmio_base + MX3_PWMSAR);

drivers/pwm/pwm-imx27.c

338

writel_relaxed(duty_cycles, imx->mmio_base + MX3_PWMSAR);

drivers/pwm/pwm-imx27.c

341

writel(period_cycles, imx->mmio_base + MX3_PWMPR);

drivers/pwm/pwm-imx27.c

361

writel(cr, imx->mmio_base + MX3_PWMCR);

drivers/pwm/pwm-imx27.c

405

imx->mmio_base = devm_platform_ioremap_resource(pdev, 0);

drivers/pwm/pwm-imx27.c

406

if (IS_ERR(imx->mmio_base))

drivers/pwm/pwm-imx27.c

407

return PTR_ERR(imx->mmio_base);

drivers/pwm/pwm-imx27.c

414

pwmcr = readl(imx->mmio_base + MX3_PWMCR);

drivers/pwm/pwm-imx27.c

89

void __iomem *mmio_base;

drivers/pwm/pwm-pxa.c

193

pc->mmio_base = devm_platform_ioremap_resource(pdev, 0);

drivers/pwm/pwm-pxa.c

194

if (IS_ERR(pc->mmio_base))

drivers/pwm/pwm-pxa.c

195

return PTR_ERR(pc->mmio_base);

drivers/pwm/pwm-pxa.c

56

void __iomem *mmio_base;

drivers/pwm/pwm-pxa.c

96

writel(prescale | PWMCR_SD, pc->mmio_base + offset + PWMCR);

drivers/pwm/pwm-pxa.c

97

writel(dc, pc->mmio_base + offset + PWMDCR);

drivers/pwm/pwm-pxa.c

98

writel(pv, pc->mmio_base + offset + PWMPCR);

drivers/pwm/pwm-spear.c

205

pc->mmio_base = devm_platform_ioremap_resource(pdev, 0);

drivers/pwm/pwm-spear.c

206

if (IS_ERR(pc->mmio_base))

drivers/pwm/pwm-spear.c

207

return PTR_ERR(pc->mmio_base);

drivers/pwm/pwm-spear.c

226

val = readl_relaxed(pc->mmio_base + PWMMCR);

drivers/pwm/pwm-spear.c

228

writel_relaxed(val, pc->mmio_base + PWMMCR);

drivers/pwm/pwm-spear.c

53

void __iomem *mmio_base;

drivers/pwm/pwm-spear.c

65

return readl_relaxed(chip->mmio_base + (num << 4) + offset);

drivers/pwm/pwm-spear.c

72

writel_relaxed(val, chip->mmio_base + (num << 4) + offset);

drivers/pwm/pwm-tiecap.c

100

value = readw(pc->mmio_base + ECCTL2);

drivers/pwm/pwm-tiecap.c

103

writew(value, pc->mmio_base + ECCTL2);

drivers/pwm/pwm-tiecap.c

119

value = readw(pc->mmio_base + ECCTL2);

drivers/pwm/pwm-tiecap.c

128

writew(value, pc->mmio_base + ECCTL2);

drivers/pwm/pwm-tiecap.c

147

value = readw(pc->mmio_base + ECCTL2);

drivers/pwm/pwm-tiecap.c

149

writew(value, pc->mmio_base + ECCTL2);

drivers/pwm/pwm-tiecap.c

163

value = readw(pc->mmio_base + ECCTL2);

drivers/pwm/pwm-tiecap.c

165

writew(value, pc->mmio_base + ECCTL2);

drivers/pwm/pwm-tiecap.c

254

pc->mmio_base = devm_platform_ioremap_resource(pdev, 0);

drivers/pwm/pwm-tiecap.c

255

if (IS_ERR(pc->mmio_base))

drivers/pwm/pwm-tiecap.c

256

return PTR_ERR(pc->mmio_base);

drivers/pwm/pwm-tiecap.c

280

pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2);

drivers/pwm/pwm-tiecap.c

281

pc->ctx.cap4 = readl(pc->mmio_base + CAP4);

drivers/pwm/pwm-tiecap.c

282

pc->ctx.cap3 = readl(pc->mmio_base + CAP3);

drivers/pwm/pwm-tiecap.c

290

writel(pc->ctx.cap3, pc->mmio_base + CAP3);

drivers/pwm/pwm-tiecap.c

291

writel(pc->ctx.cap4, pc->mmio_base + CAP4);

drivers/pwm/pwm-tiecap.c

292

writew(pc->ctx.ecctl2, pc->mmio_base + ECCTL2);

drivers/pwm/pwm-tiecap.c

40

void __iomem *mmio_base;

drivers/pwm/pwm-tiecap.c

78

value = readw(pc->mmio_base + ECCTL2);

drivers/pwm/pwm-tiecap.c

83

writew(value, pc->mmio_base + ECCTL2);

drivers/pwm/pwm-tiecap.c

87

writel(duty_cycles, pc->mmio_base + CAP2);

drivers/pwm/pwm-tiecap.c

88

writel(period_cycles, pc->mmio_base + CAP1);

drivers/pwm/pwm-tiecap.c

95

writel(duty_cycles, pc->mmio_base + CAP4);

drivers/pwm/pwm-tiecap.c

96

writel(period_cycles, pc->mmio_base + CAP3);

drivers/pwm/pwm-tiehrpwm.c

105

void __iomem *mmio_base;

drivers/pwm/pwm-tiehrpwm.c

241

ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval);

drivers/pwm/pwm-tiehrpwm.c

277

ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val);

drivers/pwm/pwm-tiehrpwm.c

280

ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW);

drivers/pwm/pwm-tiehrpwm.c

282

ehrpwm_write(pc->mmio_base, TBPRD, period_cycles - 1);

drivers/pwm/pwm-tiehrpwm.c

285

ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK,

drivers/pwm/pwm-tiehrpwm.c

289

ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles);

drivers/pwm/pwm-tiehrpwm.c

313

ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,

drivers/pwm/pwm-tiehrpwm.c

316

ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);

drivers/pwm/pwm-tiehrpwm.c

344

ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,

drivers/pwm/pwm-tiehrpwm.c

346

ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);

drivers/pwm/pwm-tiehrpwm.c

351

ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,

drivers/pwm/pwm-tiehrpwm.c

354

ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);

drivers/pwm/pwm-tiehrpwm.c

446

pc->mmio_base = devm_platform_ioremap_resource(pdev, 0);

drivers/pwm/pwm-tiehrpwm.c

447

if (IS_ERR(pc->mmio_base))

drivers/pwm/pwm-tiehrpwm.c

448

return PTR_ERR(pc->mmio_base);

drivers/pwm/pwm-tiehrpwm.c

496

pc->ctx.tbctl = ehrpwm_read(pc->mmio_base, TBCTL);

drivers/pwm/pwm-tiehrpwm.c

497

pc->ctx.tbprd = ehrpwm_read(pc->mmio_base, TBPRD);

drivers/pwm/pwm-tiehrpwm.c

498

pc->ctx.cmpa = ehrpwm_read(pc->mmio_base, CMPA);

drivers/pwm/pwm-tiehrpwm.c

499

pc->ctx.cmpb = ehrpwm_read(pc->mmio_base, CMPB);

drivers/pwm/pwm-tiehrpwm.c

500

pc->ctx.aqctla = ehrpwm_read(pc->mmio_base, AQCTLA);

drivers/pwm/pwm-tiehrpwm.c

501

pc->ctx.aqctlb = ehrpwm_read(pc->mmio_base, AQCTLB);

drivers/pwm/pwm-tiehrpwm.c

502

pc->ctx.aqsfrc = ehrpwm_read(pc->mmio_base, AQSFRC);

drivers/pwm/pwm-tiehrpwm.c

503

pc->ctx.aqcsfrc = ehrpwm_read(pc->mmio_base, AQCSFRC);

drivers/pwm/pwm-tiehrpwm.c

512

ehrpwm_write(pc->mmio_base, TBPRD, pc->ctx.tbprd);

drivers/pwm/pwm-tiehrpwm.c

513

ehrpwm_write(pc->mmio_base, CMPA, pc->ctx.cmpa);

drivers/pwm/pwm-tiehrpwm.c

514

ehrpwm_write(pc->mmio_base, CMPB, pc->ctx.cmpb);

drivers/pwm/pwm-tiehrpwm.c

515

ehrpwm_write(pc->mmio_base, AQCTLA, pc->ctx.aqctla);

drivers/pwm/pwm-tiehrpwm.c

516

ehrpwm_write(pc->mmio_base, AQCTLB, pc->ctx.aqctlb);

drivers/pwm/pwm-tiehrpwm.c

517

ehrpwm_write(pc->mmio_base, AQSFRC, pc->ctx.aqsfrc);

drivers/pwm/pwm-tiehrpwm.c

518

ehrpwm_write(pc->mmio_base, AQCSFRC, pc->ctx.aqcsfrc);

drivers/pwm/pwm-tiehrpwm.c

519

ehrpwm_write(pc->mmio_base, TBCTL, pc->ctx.tbctl);

drivers/rtc/rtc-ep93xx.c

132

ep93xx_rtc->mmio_base = devm_platform_ioremap_resource(pdev, 0);

drivers/rtc/rtc-ep93xx.c

133

if (IS_ERR(ep93xx_rtc->mmio_base))

drivers/rtc/rtc-ep93xx.c

134

return PTR_ERR(ep93xx_rtc->mmio_base);

drivers/rtc/rtc-ep93xx.c

30

void __iomem *mmio_base;

drivers/rtc/rtc-ep93xx.c

39

comp = readl(ep93xx_rtc->mmio_base + EP93XX_RTC_SWCOMP);

drivers/rtc/rtc-ep93xx.c

57

time = readl(ep93xx_rtc->mmio_base + EP93XX_RTC_DATA);

drivers/rtc/rtc-ep93xx.c

68

writel(secs + 1, ep93xx_rtc->mmio_base + EP93XX_RTC_LOAD);

drivers/scsi/megaraid.c

4219

adapter->mmio_base = (void __iomem *) mega_baseport;

drivers/scsi/megaraid.c

79

#define RDINDOOR(adapter) readl((adapter)->mmio_base + 0x20)

drivers/scsi/megaraid.c

80

#define RDOUTDOOR(adapter) readl((adapter)->mmio_base + 0x2C)

drivers/scsi/megaraid.c

81

#define WRINDOOR(adapter,value) writel(value, (adapter)->mmio_base + 0x20)

drivers/scsi/megaraid.c

82

#define WROUTDOOR(adapter,value) writel(value, (adapter)->mmio_base + 0x2C)

drivers/scsi/megaraid.h

792

void __iomem *mmio_base;

drivers/scsi/myrb.c

1240

if (cb->mmio_base) {

drivers/scsi/myrb.c

1243

iounmap(cb->mmio_base);

drivers/scsi/myrb.c

3434

cb->mmio_base = ioremap(cb->pci_addr & PAGE_MASK, mmio_size);

drivers/scsi/myrb.c

3435

if (cb->mmio_base == NULL) {

drivers/scsi/myrb.c

3441

cb->io_base = cb->mmio_base + (cb->pci_addr & ~PAGE_MASK);

drivers/scsi/myrb.h

739

void __iomem *mmio_base;

drivers/scsi/myrs.c

2269

if (cs->mmio_base) {

drivers/scsi/myrs.c

2272

iounmap(cs->mmio_base);

drivers/scsi/myrs.c

2273

cs->mmio_base = NULL;

drivers/scsi/myrs.c

2310

cs->mmio_base = ioremap(cs->pci_addr & PAGE_MASK, mmio_size);

drivers/scsi/myrs.c

2311

if (cs->mmio_base == NULL) {

drivers/scsi/myrs.c

2317

cs->io_base = cs->mmio_base + (cs->pci_addr & ~PAGE_MASK);

drivers/scsi/myrs.h

889

void __iomem *mmio_base;

drivers/scsi/pcmcia/nsp_cs.c

719

unsigned long mmio_base = SCpnt->device->host->base;

drivers/scsi/pcmcia/nsp_cs.c

773

nsp_mmio_fifo32_read(mmio_base, scsi_pointer->ptr,

drivers/scsi/pcmcia/nsp_cs.c

822

unsigned long mmio_base = SCpnt->device->host->base;

drivers/scsi/pcmcia/nsp_cs.c

876

nsp_mmio_fifo32_write(mmio_base, scsi_pointer->ptr,

drivers/scsi/stex.c

1027

void __iomem *base = hba->mmio_base;

drivers/scsi/stex.c

1111

void __iomem *base = hba->mmio_base;

drivers/scsi/stex.c

1259

base = hba->mmio_base;

drivers/scsi/stex.c

1353

base = hba->mmio_base;

drivers/scsi/stex.c

1380

writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);

drivers/scsi/stex.c

1381

readl(hba->mmio_base + YH2I_INT);

drivers/scsi/stex.c

1387

writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);

drivers/scsi/stex.c

1689

hba->mmio_base = pci_ioremap_bar(pdev, 0);

drivers/scsi/stex.c

1690

if ( !hba->mmio_base) {

drivers/scsi/stex.c

1841

iounmap(hba->mmio_base);

drivers/scsi/stex.c

1921

iounmap(hba->mmio_base);

drivers/scsi/stex.c

314

void __iomem *mmio_base; /* iomapped PCI memory space */

drivers/scsi/stex.c

525

writel(hba->req_head, hba->mmio_base + IMR0);

drivers/scsi/stex.c

526

writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);

drivers/scsi/stex.c

527

readl(hba->mmio_base + IDBL); /* flush */

drivers/scsi/stex.c

555

writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);

drivers/scsi/stex.c

556

writel(addr, hba->mmio_base + YH2I_REQ);

drivers/scsi/stex.c

558

writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);

drivers/scsi/stex.c

559

readl(hba->mmio_base + YH2I_REQ_HI); /* flush */

drivers/scsi/stex.c

560

writel(addr, hba->mmio_base + YH2I_REQ);

drivers/scsi/stex.c

561

readl(hba->mmio_base + YH2I_REQ); /* flush */

drivers/scsi/stex.c

798

void __iomem *base = hba->mmio_base;

drivers/scsi/stex.c

886

void __iomem *base = hba->mmio_base;

drivers/scsi/stex.c

987

void __iomem *base = hba->mmio_base;

drivers/scsi/sym53c8xx_2/sym_glue.c

1335

np->mmio_ba = (u32)dev->mmio_base;

drivers/scsi/sym53c8xx_2/sym_glue.c

1563

device->mmio_base = bus_addr.start;

drivers/scsi/sym53c8xx_2/sym_glue.c

1578

if (device->mmio_base)

drivers/scsi/sym53c8xx_2/sym_glue.h

193

unsigned long mmio_base;

drivers/soc/pxa/ssp.c

142

ssp->mmio_base = devm_ioremap(dev, res->start, resource_size(res));

drivers/soc/pxa/ssp.c

143

if (ssp->mmio_base == NULL) {

drivers/soundwire/amd_init.c

91

ret = amd_enable_sdw_pads(res->mmio_base, res->link_mask, res->parent);

drivers/soundwire/intel.h

34

void __iomem *mmio_base; /* not strictly needed, useful for debug */

drivers/soundwire/intel_init.c

207

ctx->mmio_base = res->mmio_base;

drivers/soundwire/intel_init.c

66

link->mmio_base = res->mmio_base;

drivers/soundwire/intel_init.c

68

link->registers = res->mmio_base + SDW_LINK_BASE

drivers/soundwire/intel_init.c

71

link->shim = res->mmio_base + res->shim_base;

drivers/soundwire/intel_init.c

72

link->alh = res->mmio_base + res->alh_base;

drivers/soundwire/intel_init.c

75

link->registers = res->mmio_base + SDW_IP_BASE(link_id);

drivers/soundwire/intel_init.c

77

link->shim = res->mmio_base + SDW_SHIM2_GENERIC_BASE(link_id);

drivers/soundwire/intel_init.c

78

link->shim_vs = res->mmio_base + SDW_SHIM2_VS_BASE(link_id);

drivers/spi/spi-pxa2xx-pci.c

283

ssp->mmio_base = pcim_iomap_region(dev, 0, "PXA2xx SPI");

drivers/spi/spi-pxa2xx-pci.c

284

if (IS_ERR(ssp->mmio_base))

drivers/spi/spi-pxa2xx-pci.c

285

return PTR_ERR(ssp->mmio_base);

drivers/spi/spi-pxa2xx-platform.c

29

ssp->mmio_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);

drivers/spi/spi-pxa2xx-platform.c

30

if (IS_ERR(ssp->mmio_base))

drivers/spi/spi-pxa2xx-platform.c

31

return PTR_ERR(ssp->mmio_base);

drivers/spi/spi-pxa2xx.c

352

drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset;

drivers/thermal/intel/int340x_thermal/platform_temperature_control.c

110

reg_val = readq((void __iomem *) (proc_priv->mmio_base + data->offset));

drivers/thermal/intel/int340x_thermal/platform_temperature_control.c

139

reg_val = readq((void __iomem *) (proc_priv->mmio_base + offset));

drivers/thermal/intel/int340x_thermal/platform_temperature_control.c

142

writeq(reg_val, (void __iomem *) (proc_priv->mmio_base + offset));

drivers/thermal/intel/int340x_thermal/processor_thermal_device.c

387

proc_priv->mmio_base = pcim_iomap_table(pdev)[MCHBAR];

drivers/thermal/intel/int340x_thermal/processor_thermal_device.h

54

void __iomem *mmio_base;

drivers/thermal/intel/int340x_thermal/processor_thermal_device_pci.c

107

iowrite32(current_val, ((u8 __iomem *)pci_info->proc_priv->mmio_base +

drivers/thermal/intel/int340x_thermal/processor_thermal_device_pci.c

145

status = readq(proc_priv->mmio_base + SOC_WT_RES_INT_STATUS_OFFSET);

drivers/thermal/intel/int340x_thermal/processor_thermal_device_pci.c

147

proc_priv->mmio_base + SOC_WT_RES_INT_STATUS_OFFSET);

drivers/thermal/intel/int340x_thermal/processor_thermal_device_pci.c

85

*value = ioread32(((u8 __iomem *)pci_info->proc_priv->mmio_base +

drivers/thermal/intel/int340x_thermal/processor_thermal_device_pci.c

98

current_val = ioread32(((u8 __iomem *)pci_info->proc_priv->mmio_base +

drivers/thermal/intel/int340x_thermal/processor_thermal_mbox.c

29

data = readl(proc_priv->mmio_base + MBOX_OFFSET_INTERFACE);

drivers/thermal/intel/int340x_thermal/processor_thermal_mbox.c

52

writel(data, (proc_priv->mmio_base + MBOX_OFFSET_DATA));

drivers/thermal/intel/int340x_thermal/processor_thermal_mbox.c

55

writel(reg_data, (proc_priv->mmio_base + MBOX_OFFSET_INTERFACE));

drivers/thermal/intel/int340x_thermal/processor_thermal_mbox.c

73

writel(reg_data, (proc_priv->mmio_base + MBOX_OFFSET_INTERFACE));

drivers/thermal/intel/int340x_thermal/processor_thermal_mbox.c

80

*resp = readl(proc_priv->mmio_base + MBOX_OFFSET_DATA);

drivers/thermal/intel/int340x_thermal/processor_thermal_mbox.c

82

*resp = readq(proc_priv->mmio_base + MBOX_OFFSET_DATA);

drivers/thermal/intel/int340x_thermal/processor_thermal_power_floor.c

117

status = readq(proc_priv->mmio_base + SOC_WT_RES_INT_STATUS_OFFSET);

drivers/thermal/intel/int340x_thermal/processor_thermal_power_floor.c

42

status = readq(proc_priv->mmio_base + SOC_WT_RES_INT_STATUS_OFFSET);

drivers/thermal/intel/int340x_thermal/processor_thermal_power_floor.c

94

int_status = readq(proc_priv->mmio_base + SOC_WT_RES_INT_STATUS_OFFSET);

drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c

61

proc_priv->mmio_base +

drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c

66

rapl_mmio_priv.reg_unit.mmio = proc_priv->mmio_base + rapl_regs->reg_unit;

drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c

211

reg_val = readl((void __iomem *) (proc_priv->mmio_base + mmio_regs[ret].offset));\

drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c

261

reg_val = readl((void __iomem *) (proc_priv->mmio_base + mmio_regs[ret].offset));\

drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c

264

writel(reg_val, (void __iomem *) (proc_priv->mmio_base + mmio_regs[ret].offset));\

drivers/thermal/intel/int340x_thermal/processor_thermal_soc_slider.c

167

return readq(proc_priv->mmio_base + SOC_POWER_SLIDER_OFFSET);

drivers/thermal/intel/int340x_thermal/processor_thermal_soc_slider.c

172

writeq(val, proc_priv->mmio_base + SOC_POWER_SLIDER_OFFSET);

drivers/thermal/intel/int340x_thermal/processor_thermal_wt_hint.c

242

int_status = readq(proc_priv->mmio_base + SOC_WT_RES_INT_STATUS_OFFSET);

drivers/thermal/intel/int340x_thermal/processor_thermal_wt_hint.c

255

status = readq(proc_priv->mmio_base + SOC_WT_RES_INT_STATUS_OFFSET);

drivers/thermal/intel/int340x_thermal/processor_thermal_wt_hint.c

71

status = readq(proc_priv->mmio_base + SOC_WT_RES_INT_STATUS_OFFSET);

drivers/thermal/st/st_thermal.h

92

void __iomem *mmio_base;

drivers/thermal/st/st_thermal_memmap.c

123

sensor->mmio_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);

drivers/thermal/st/st_thermal_memmap.c

124

if (IS_ERR(sensor->mmio_base))

drivers/thermal/st/st_thermal_memmap.c

125

return PTR_ERR(sensor->mmio_base);

drivers/thermal/st/st_thermal_memmap.c

127

sensor->regmap = devm_regmap_init_mmio(dev, sensor->mmio_base,

drivers/thermal/thermal_mmio.c

12

void __iomem *mmio_base;

drivers/thermal/thermal_mmio.c

13

u32 (*read_mmio)(void __iomem *mmio_base);

drivers/thermal/thermal_mmio.c

18

static u32 thermal_mmio_readb(void __iomem *mmio_base)

drivers/thermal/thermal_mmio.c

20

return readb(mmio_base);

drivers/thermal/thermal_mmio.c

28

t = sensor->read_mmio(sensor->mmio_base) & sensor->mask;

drivers/thermal/thermal_mmio.c

53

sensor->mmio_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);

drivers/thermal/thermal_mmio.c

54

if (IS_ERR(sensor->mmio_base))

drivers/thermal/thermal_mmio.c

55

return PTR_ERR(sensor->mmio_base);

drivers/ufs/core/ufshcd.c

10832

int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)

drivers/ufs/core/ufshcd.c

10845

if (!mmio_base) {

drivers/ufs/core/ufshcd.c

10852

hba->mmio_base = mmio_base;

drivers/ufs/host/tc-dwc-g210-pci.c

60

void __iomem *mmio_base;

drivers/ufs/host/tc-dwc-g210-pci.c

83

mmio_base = pcim_iomap_region(pdev, 0, UFSHCD);

drivers/ufs/host/tc-dwc-g210-pci.c

84

if (IS_ERR(mmio_base)) {

drivers/ufs/host/tc-dwc-g210-pci.c

86

return PTR_ERR(mmio_base);

drivers/ufs/host/tc-dwc-g210-pci.c

97

err = ufshcd_init(hba, mmio_base, pdev->irq);

drivers/ufs/host/ufs-mediatek.c

2200

opr->base = hba->mmio_base + opr->offset;

drivers/ufs/host/ufs-mediatek.c

2216

hba->mcq_base = hba->mmio_base + MCQ_QUEUE_OFFSET(hba->mcq_capabilities);

drivers/ufs/host/ufs-qcom.c

1422

host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;

drivers/ufs/host/ufs-renesas.c

47

ret = readl_poll_timeout_atomic(hba->mmio_base + reg,

drivers/ufs/host/ufshcd-pci.c

229

host->active_ltr = readl(hba->mmio_base + INTEL_ACTIVELTR);

drivers/ufs/host/ufshcd-pci.c

230

host->idle_ltr = readl(hba->mmio_base + INTEL_IDLELTR);

drivers/ufs/host/ufshcd-pci.c

246

ltr = readl(hba->mmio_base + INTEL_ACTIVELTR);

drivers/ufs/host/ufshcd-pci.c

268

writel(ltr, hba->mmio_base + INTEL_ACTIVELTR);

drivers/ufs/host/ufshcd-pci.c

269

writel(ltr, hba->mmio_base + INTEL_IDLELTR);

drivers/ufs/host/ufshcd-pci.c

452

hba->mcq_base = hba->mmio_base + ufshcd_mcq_queue_cfg_addr(hba);

drivers/ufs/host/ufshcd-pci.c

475

opr->base = hba->mmio_base + opr->offset;

drivers/ufs/host/ufshcd-pci.c

632

void __iomem *mmio_base;

drivers/ufs/host/ufshcd-pci.c

643

mmio_base = pcim_iomap_region(pdev, 0, UFSHCD);

drivers/ufs/host/ufshcd-pci.c

644

if (IS_ERR(mmio_base)) {

drivers/ufs/host/ufshcd-pci.c

646

return PTR_ERR(mmio_base);

drivers/ufs/host/ufshcd-pci.c

657

err = ufshcd_init(hba, mmio_base, pdev->irq);

drivers/ufs/host/ufshcd-pltfrm.c

496

void __iomem *mmio_base;

drivers/ufs/host/ufshcd-pltfrm.c

500

mmio_base = devm_platform_ioremap_resource(pdev, 0);

drivers/ufs/host/ufshcd-pltfrm.c

501

if (IS_ERR(mmio_base))

drivers/ufs/host/ufshcd-pltfrm.c

502

return PTR_ERR(mmio_base);

drivers/ufs/host/ufshcd-pltfrm.c

537

err = ufshcd_init(hba, mmio_base, irq);

drivers/usb/host/ohci-pxa27x.c

120

void __iomem *mmio_base;

drivers/usb/host/ohci-pxa27x.c

139

uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);

drivers/usb/host/ohci-pxa27x.c

140

uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB);

drivers/usb/host/ohci-pxa27x.c

164

__raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);

drivers/usb/host/ohci-pxa27x.c

165

__raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB);

drivers/usb/host/ohci-pxa27x.c

220

uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);

drivers/usb/host/ohci-pxa27x.c

221

uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);

drivers/usb/host/ohci-pxa27x.c

253

__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);

drivers/usb/host/ohci-pxa27x.c

254

__raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);

drivers/usb/host/ohci-pxa27x.c

259

uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);

drivers/usb/host/ohci-pxa27x.c

261

__raw_writel(uhchr | UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);

drivers/usb/host/ohci-pxa27x.c

263

__raw_writel(uhchr & ~UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);

drivers/usb/host/ohci-pxa27x.c

280

uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) | UHCHR_FSBIR;

drivers/usb/host/ohci-pxa27x.c

281

__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);

drivers/usb/host/ohci-pxa27x.c

283

while (__raw_readl(pxa_ohci->mmio_base + UHCHR) & UHCHR_FSBIR)

drivers/usb/host/ohci-pxa27x.c

296

uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE;

drivers/usb/host/ohci-pxa27x.c

297

__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);

drivers/usb/host/ohci-pxa27x.c

298

__raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, pxa_ohci->mmio_base + UHCHIE);

drivers/usb/host/ohci-pxa27x.c

318

uhccoms = __raw_readl(pxa_ohci->mmio_base + UHCCOMS) | 0x01;

drivers/usb/host/ohci-pxa27x.c

319

__raw_writel(uhccoms, pxa_ohci->mmio_base + UHCCOMS);

drivers/usb/host/ohci-pxa27x.c

448

pxa_ohci->mmio_base = (void __iomem *)hcd->regs;

drivers/video/fbdev/asiliantfb.c

218

writeb(0xc7, mmio_base + 0x784); /* set misc output reg */

drivers/video/fbdev/asiliantfb.c

220

writeb(0x07, mmio_base + 0x784); /* set misc output reg */

drivers/video/fbdev/asiliantfb.c

318

writeb(regno, mmio_base + 0x790);

drivers/video/fbdev/asiliantfb.c

320

writeb(red, mmio_base + 0x791);

drivers/video/fbdev/asiliantfb.c

321

writeb(green, mmio_base + 0x791);

drivers/video/fbdev/asiliantfb.c

322

writeb(blue, mmio_base + 0x791);

drivers/video/fbdev/asiliantfb.c

472

writeb(0x20, mmio_base + 0x780);

drivers/video/fbdev/asiliantfb.c

52

writeb((num), mmio_base + (ap)); writeb((val), mmio_base + (dp)); \

drivers/video/fbdev/asiliantfb.c

534

writeb(0xff, mmio_base + 0x78c);

drivers/video/fbdev/asiliantfb.c

87

readb(mmio_base + 0x7b4);

drivers/video/fbdev/aty/radeon_base.c

2312

rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);

drivers/video/fbdev/aty/radeon_base.c

2313

if (!rinfo->mmio_base) {

drivers/video/fbdev/aty/radeon_base.c

2490

iounmap(rinfo->mmio_base);

drivers/video/fbdev/aty/radeon_base.c

2524

iounmap(rinfo->mmio_base);

drivers/video/fbdev/aty/radeonfb.h

299

void __iomem *mmio_base;

drivers/video/fbdev/aty/radeonfb.h

376

#define INREG8(addr) readb((rinfo->mmio_base)+addr)

drivers/video/fbdev/aty/radeonfb.h

377

#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)

drivers/video/fbdev/aty/radeonfb.h

378

#define INREG16(addr) readw((rinfo->mmio_base)+addr)

drivers/video/fbdev/aty/radeonfb.h

379

#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)

drivers/video/fbdev/aty/radeonfb.h

380

#define INREG(addr) readl((rinfo->mmio_base)+addr)

drivers/video/fbdev/aty/radeonfb.h

381

#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)

drivers/video/fbdev/ep93xx-fb.c

113

void __iomem *mmio_base;

drivers/video/fbdev/ep93xx-fb.c

125

return __raw_readl(fbi->mmio_base + off);

drivers/video/fbdev/ep93xx-fb.c

131

__raw_writel(val, fbi->mmio_base + off);

drivers/video/fbdev/ep93xx-fb.c

506

fbi->mmio_base = devm_ioremap(&pdev->dev, res->start,

drivers/video/fbdev/ep93xx-fb.c

508

if (!fbi->mmio_base) {

drivers/video/fbdev/mb862xx/mb862xxfb.h

59

void __iomem *mmio_base; /* remapped registers */

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

1062

par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

1063

if (par->mmio_base == NULL) {

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

1119

iounmap(par->mmio_base);

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

1160

iounmap(par->mmio_base);

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

624

par->host = par->mmio_base;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

625

par->i2c = par->mmio_base + MB862XX_I2C_BASE;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

626

par->disp = par->mmio_base + MB862XX_DISP_BASE;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

627

par->cap = par->mmio_base + MB862XX_CAP_BASE;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

628

par->draw = par->mmio_base + MB862XX_DRAW_BASE;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

629

par->geo = par->mmio_base + MB862XX_GEO_BASE;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

630

par->pio = par->mmio_base + MB862XX_PIO_BASE;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

725

par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

726

if (par->mmio_base == NULL) {

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

772

iounmap(par->mmio_base);

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

809

iounmap(par->mmio_base);

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

846

par->host = par->mmio_base;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

847

par->i2c = par->mmio_base + MB862XX_I2C_BASE;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

848

par->disp = par->mmio_base + MB862XX_DISP_BASE;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

849

par->cap = par->mmio_base + MB862XX_CAP_BASE;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

850

par->draw = par->mmio_base + MB862XX_DRAW_BASE;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

851

par->geo = par->mmio_base + MB862XX_GEO_BASE;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

852

par->pio = par->mmio_base + MB862XX_PIO_BASE;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

927

par->ctrl = par->mmio_base + MB86297_CTRL_BASE;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

928

par->i2c = par->mmio_base + MB86297_I2C_BASE;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

929

par->disp = par->mmio_base + MB86297_DISP0_BASE;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

930

par->disp1 = par->mmio_base + MB86297_DISP1_BASE;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

931

par->cap = par->mmio_base + MB86297_CAP0_BASE;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

932

par->cap1 = par->mmio_base + MB86297_CAP1_BASE;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

933

par->draw = par->mmio_base + MB86297_DRAW_BASE;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

934

par->dram_ctrl = par->mmio_base + MB86297_DRAMCTRL_BASE;

drivers/video/fbdev/mb862xx/mb862xxfbdrv.c

935

par->wrback = par->mmio_base + MB86297_WRBACK_BASE;

drivers/video/fbdev/pvr2fb.c

144

void __iomem *mmio_base; /* MMIO base */

drivers/video/fbdev/pvr2fb.c

234

fb_writel(type, par->mmio_base + 0x108);

drivers/video/fbdev/pvr2fb.c

241

fb_writel(val, par->mmio_base + 0x1000 + (4 * regno));

drivers/video/fbdev/pvr2fb.c

799

par->mmio_base = ioremap(pvr2_fix.mmio_start,

drivers/video/fbdev/pvr2fb.c

801

if (!par->mmio_base) {

drivers/video/fbdev/pvr2fb.c

82

#define DISP_BASE par->mmio_base

drivers/video/fbdev/pvr2fb.c

838

rev = fb_readl(par->mmio_base + 0x04);

drivers/video/fbdev/pvr2fb.c

866

if (par->mmio_base)

drivers/video/fbdev/pvr2fb.c

867

iounmap(par->mmio_base);

drivers/video/fbdev/pvr2fb.c

933

if (currentpar->mmio_base) {

drivers/video/fbdev/pvr2fb.c

934

iounmap(currentpar->mmio_base);

drivers/video/fbdev/pvr2fb.c

935

currentpar->mmio_base = NULL;

drivers/video/fbdev/pvr2fb.c

987

if (currentpar->mmio_base) {

drivers/video/fbdev/pvr2fb.c

988

iounmap(currentpar->mmio_base);

drivers/video/fbdev/pvr2fb.c

989

currentpar->mmio_base = NULL;

drivers/video/fbdev/pxa3xx-gcu.c

106

return __raw_readl(priv->mmio_base + off);

drivers/video/fbdev/pxa3xx-gcu.c

112

__raw_writel(val, priv->mmio_base + off);

drivers/video/fbdev/pxa3xx-gcu.c

602

priv->mmio_base = devm_platform_get_and_ioremap_resource(pdev, 0, &r);

drivers/video/fbdev/pxa3xx-gcu.c

603

if (IS_ERR(priv->mmio_base))

drivers/video/fbdev/pxa3xx-gcu.c

604

return PTR_ERR(priv->mmio_base);

drivers/video/fbdev/pxa3xx-gcu.c

86

void __iomem *mmio_base;

drivers/video/fbdev/pxafb.c

105

__raw_writel(val, fbi->mmio_base + off);

drivers/video/fbdev/pxafb.c

2284

fbi->mmio_base = devm_platform_ioremap_resource(dev, 0);

drivers/video/fbdev/pxafb.c

2285

if (IS_ERR(fbi->mmio_base)) {

drivers/video/fbdev/pxafb.c

2287

ret = PTR_ERR(fbi->mmio_base);

drivers/video/fbdev/pxafb.c

99

return __raw_readl(fbi->mmio_base + off);

drivers/video/fbdev/pxafb.h

114

void __iomem *mmio_base;

drivers/video/fbdev/sis/sis.h

515

unsigned long mmio_base;

drivers/video/fbdev/sis/sis_main.c

1860

fix->mmio_start = ivideo->mmio_base;

drivers/video/fbdev/sis/sis_main.c

6005

ivideo->mmio_base = pci_resource_start(pdev, 1);

drivers/video/fbdev/sis/sis_main.c

6184

if(!request_mem_region(ivideo->mmio_base, ivideo->mmio_size, "sisfb MMIO")) {

drivers/video/fbdev/sis/sis_main.c

6198

ivideo->mmio_vbase = ioremap(ivideo->mmio_base, ivideo->mmio_size);

drivers/video/fbdev/sis/sis_main.c

6204

error_2: release_mem_region(ivideo->mmio_base, ivideo->mmio_size);

drivers/video/fbdev/sis/sis_main.c

6223

ivideo->mmio_base, (unsigned long)ivideo->mmio_vbase, ivideo->mmio_size / 1024);

drivers/video/fbdev/sis/sis_main.c

6492

release_mem_region(ivideo->mmio_base, ivideo->mmio_size);

drivers/video/fbdev/sm712fb.c

1500

unsigned long mmio_base;

drivers/video/fbdev/sm712fb.c

1541

mmio_base = pci_resource_start(pdev, 0);

drivers/video/fbdev/sm712fb.c

1551

sfb->fb->fix.mmio_start = mmio_base + 0x00400000;

drivers/video/fbdev/sm712fb.c

1553

sfb->lfb = ioremap(mmio_base, mmio_addr);

drivers/video/fbdev/sm712fb.c

1582

sfb->fb->fix.mmio_start = mmio_base;

drivers/video/fbdev/sm712fb.c

1584

sfb->dp_regs = ioremap(mmio_base, 0x00200000 + smem_size);

drivers/video/fbdev/vt8623fb.c

31

char __iomem *mmio_base;

drivers/video/fbdev/vt8623fb.c

727

par->mmio_base = pci_iomap(dev, 1, 0);

drivers/video/fbdev/vt8623fb.c

728

if (! par->mmio_base) {

drivers/video/fbdev/vt8623fb.c

802

pci_iounmap(dev, par->mmio_base);

drivers/video/fbdev/vt8623fb.c

828

pci_iounmap(dev, par->mmio_base);

include/linux/pxa2xx_ssp.h

240

void __iomem *mmio_base;

include/linux/pxa2xx_ssp.h

261

__raw_writel(val, dev->mmio_base + reg);

include/linux/pxa2xx_ssp.h

272

return __raw_readl(dev->mmio_base + reg);

include/linux/soundwire/sdw_amd.h

159

void __iomem *mmio_base;

include/linux/soundwire/sdw_intel.h

305

void __iomem *mmio_base;

include/linux/soundwire/sdw_intel.h

345

void __iomem *mmio_base;

include/ufs/ufshcd.h

1276

writel((val), (hba)->mmio_base + (reg))

include/ufs/ufshcd.h

1278

readl((hba)->mmio_base + (reg))

include/ufs/ufshcd.h

949

void __iomem *mmio_base;

sound/soc/amd/ps/pci-ps.c

291

sdw_res.mmio_base = acp_data->acp63_base;

sound/soc/pxa/pxa-ssp.c

126

priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);

sound/soc/pxa/pxa-ssp.c

127

priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);

sound/soc/pxa/pxa-ssp.c

128

priv->to = __raw_readl(ssp->mmio_base + SSTO);

sound/soc/pxa/pxa-ssp.c

129

priv->psp = __raw_readl(ssp->mmio_base + SSPSP);

sound/soc/pxa/pxa-ssp.c

144

__raw_writel(sssr, ssp->mmio_base + SSSR);

sound/soc/pxa/pxa-ssp.c

145

__raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);

sound/soc/pxa/pxa-ssp.c

146

__raw_writel(priv->cr1, ssp->mmio_base + SSCR1);

sound/soc/pxa/pxa-ssp.c

147

__raw_writel(priv->to, ssp->mmio_base + SSTO);

sound/soc/pxa/pxa-ssp.c

148

__raw_writel(priv->psp, ssp->mmio_base + SSPSP);

sound/soc/sof/amd/acp.c

795

sdw_res.mmio_base = sdev->bar[ACP_DSP_BAR];

sound/soc/sof/intel/hda.c

172

res.mmio_base = sdev->bar[HDA_DSP_BAR];

sound/soc/sof/intel/hda.c

188

res.mmio_base = sdev->bar[HDA_DSP_HDA_BAR];

sound/soc/xilinx/xlnx_formatter_pcm.c

247

static int xlnx_formatter_pcm_reset(void __iomem *mmio_base)

sound/soc/xilinx/xlnx_formatter_pcm.c

251

val = readl(mmio_base + XLNX_AUD_CTRL);

sound/soc/xilinx/xlnx_formatter_pcm.c

253

writel(val, mmio_base + XLNX_AUD_CTRL);

sound/soc/xilinx/xlnx_formatter_pcm.c

255

val = readl(mmio_base + XLNX_AUD_CTRL);

sound/soc/xilinx/xlnx_formatter_pcm.c

260

val = readl(mmio_base + XLNX_AUD_CTRL);

sound/soc/xilinx/xlnx_formatter_pcm.c

268

static void xlnx_formatter_disable_irqs(void __iomem *mmio_base, int stream)

sound/soc/xilinx/xlnx_formatter_pcm.c

272

val = readl(mmio_base + XLNX_AUD_CTRL);

sound/soc/xilinx/xlnx_formatter_pcm.c

277

writel(val, mmio_base + XLNX_AUD_CTRL);

tools/power/x86/turbostat/turbostat.c

10152

new_pmt->mmio_base = mmio;

tools/power/x86/turbostat/turbostat.c

10201

ret = (char *)pmmio->mmio_base;

tools/power/x86/turbostat/turbostat.c

1938

void *mmio_base;