mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR
mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR :
lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,