Symbol: mmVGT_ESGS_RING_SIZE_Sienna_Cichlid
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
7295
data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
7296
WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
7299
if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
7303
WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
7383
(SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<