mmVCE_VCPU_CNTL
WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK,
WREG32_P(mmVCE_VCPU_CNTL, 0, ~VCE_VCPU_CNTL__CLK_EN_MASK);
WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x80001);
WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001);
WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x200001);
WREG32_OR(mmVCE_VCPU_CNTL, 0x00100000);
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL),
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 1, ~0x200001);
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 0, ~0x200001);