drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

175

tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

177

WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

304

WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

481

tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

484

WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

494

tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

497

WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

157

tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

160

WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

173

WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

325

tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

327

WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

340

tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

343

WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

371

orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

375

WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

187

data = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

190

WREG32(mmVCE_UENC_CLOCK_GATING, data);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

213

data = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

215

WREG32(mmVCE_UENC_CLOCK_GATING, data);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

559

WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

794

data = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

797

WREG32(mmVCE_UENC_CLOCK_GATING, data);

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

641

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), 0x1FF000, ~0xFF9FF000);