mmVCE_STATUS
if (RREG32(mmVCE_STATUS) & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK)
(RREG32(mmVCE_STATUS) & (VCE_STATUS__JOB_BUSY_MASK | VCE_STATUS__UENC_BUSY_MASK)) ||
WREG32_P(mmVCE_STATUS, 1, ~1);
WREG32(mmVCE_STATUS, 0);
RREG32(mmVCE_STATUS), RREG32(mmSRBM_STATUS2));
WREG32(mmVCE_STATUS, 0);
uint32_t status = RREG32(mmVCE_STATUS);
WREG32_P(mmVCE_STATUS, 1, ~1);
WREG32_P(mmVCE_STATUS, 0, ~1);
WREG32(mmVCE_STATUS, 0);
uint32_t status = RREG32(mmVCE_STATUS);
WREG32(mmVCE_STATUS, 0);
if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS));
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),
MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), VCE_STATUS__JOB_BUSY_MASK,
WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK);
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0);