mmUVD_VCPU_CNTL
WREG32(mmUVD_VCPU_CNTL, 1 << 9);
WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9));
WREG32(mmUVD_VCPU_CNTL, 1 << 9);
WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9));
WREG32(mmUVD_VCPU_CNTL, 1 << 9);
WREG32(mmUVD_VCPU_CNTL, 0x0);
WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
WREG32(mmUVD_VCPU_CNTL, 0x0);
WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL,
WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0);
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,