mmUVD_VCPU_CACHE_SIZE2
WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2,
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2),
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE2),
WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
mmUVD_VCPU_CACHE_SIZE2),
WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);