mmUVD_VCPU_CACHE_OFFSET1
WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);
WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);
WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21));
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,
SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1),
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET1),
WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0);
VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
mmUVD_VCPU_CACHE_OFFSET1),
WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0);
VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);