mmUVD_VCPU_CACHE_OFFSET0
WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0);
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0,
WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0);
SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0),
WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0,
VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
VCN, 0, mmUVD_VCPU_CACHE_OFFSET0),
mmUVD_VCPU_CACHE_OFFSET0),
mmUVD_VCPU_CACHE_OFFSET0),
WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0);
WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0,
VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),