CLOCK_CNTL
DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),\
DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),\
DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0),\
DCCG_SRII(DTO_PARAM, DPPCLK, 3), DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0), \
DCCG_SRII(DTO_PARAM, DPPCLK, 3), DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0), \
aty_ld_le32(CLOCK_CNTL, par));
clock_cntl = aty_ld_8(CLOCK_CNTL, par);
aty_st_le32(CLOCK_CNTL, 0x12345678, par);
clock_r = aty_ld_le32(CLOCK_CNTL, par);
aty_st_8(CLOCK_CNTL, par->clk_wr_offset | CLOCK_STROBE, par);
clock = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
tmp = aty_ld_8(CLOCK_CNTL, par);
aty_st_8(CLOCK_CNTL + par->clk_wr_offset,
tmp = aty_ld_8(CLOCK_CNTL, par);
aty_st_8(CLOCK_CNTL + par->clk_wr_offset, (tmp & ~0x08) | (0 << 3),
tmp = aty_ld_8(CLOCK_CNTL, par);
aty_st_8(CLOCK_CNTL + par->clk_wr_offset, (tmp & ~0x08) | (1 << 3),
old_clock_cntl = aty_ld_8(CLOCK_CNTL, par);
aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 0, par);
aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 0, par); /* Strobe = 0 */
aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 1, par); /* Strobe = 0 */
aty_st_8(CLOCK_CNTL + par->clk_wr_offset,
aty_st_8(CLOCK_CNTL + par->clk_wr_offset,
tmp = aty_ld_8(CLOCK_CNTL, par);
aty_st_8(CLOCK_CNTL + par->clk_wr_offset, tmp | CLOCK_STROBE, par);
#define CLOCK_CNTL_ADDR CLOCK_CNTL + 1
#define CLOCK_CNTL_DATA CLOCK_CNTL + 2