drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

873

WREG32(mmUVD_RB_SIZE, ring->ring_size / 4);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1122

WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

927

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1001

WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1330

WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

72

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1160

WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1331

WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

2062

SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE),

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

81

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1326

WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1505

SOC15_REG_OFFSET(VCN, i, mmUVD_RB_SIZE),

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1694

WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

84

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1364

WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1505

mmUVD_RB_SIZE),

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1758

WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

88

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),