mmUVD_MPC_SET_MUXA0
WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040);
WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXA0,
WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
UVD, 0, mmUVD_MPC_SET_MUXA0),
VCN, 0, mmUVD_MPC_SET_MUXA0),
WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,
VCN, inst_idx, mmUVD_MPC_SET_MUXA0),
WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,