mmUVD_MASTINT_EN
WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));
WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));
WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1));
WREG32_P(mmUVD_MASTINT_EN,
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN),
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0,
WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
UVD, 0, mmUVD_MASTINT_EN),
VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
VCN, 0, mmUVD_MASTINT_EN),
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),
VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);
VCN, inst_idx, mmUVD_MASTINT_EN),
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),