mmUVD_CONTEXT_ID
amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
tmp = RREG32(mmUVD_CONTEXT_ID);
amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
tmp = RREG32(mmUVD_CONTEXT_ID);
amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
tmp = RREG32(mmUVD_CONTEXT_ID);
tmp = RREG32(mmUVD_CONTEXT_ID);
amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD);
PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID);
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),