drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

157

WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

206

for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

269

WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

407

WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

456

for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

653

WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

393

WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

442

for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

577

WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

267

WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

308

for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

486

WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

290

WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

331

for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

521

WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

418

WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

467

for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

603

WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);